With Particular Manufacturing Method Of Channel, E.g., Channel Implants, Halo Or Pocket Implants, Or Channel Materials (epo) Patents (Class 257/E21.633)
  • Patent number: 10636879
    Abstract: A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, and a first superlattice extending between the source and drain regions in the channel region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may be over the first superlattice and between the source and drain regions.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 28, 2020
    Assignee: ATOMERA INCORPORATED
    Inventor: Kalipatnam Vivek Rao
  • Patent number: 10593761
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10587263
    Abstract: Provided are a load drive apparatus in which a semiconductor chip using DTI for inter-element separation is mounted, the load drive apparatus being capable of diagnosing a dielectric strength voltage of the DTI and highly reliable and a failure diagnosis method of the load drive apparatus. There is provided a load drive apparatus in which a semiconductor chip is mounted. The semiconductor chip includes a load drive output unit formed on a semiconductor substrate. The load drive output unit has a first region where an MOSFET that controls load driving is formed and a second region insulated and separated by DTI from the first region and includes a first leakage current detection element provided in the first region, a second leakage current detection element provided in the second region, and a failure detection unit that determines a failure of the load drive output unit.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 10, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takahiro Kawata, Yoichiro Kobayashi, Mitsuhiko Watanabe
  • Patent number: 10361277
    Abstract: Low resistivity, wrap-around contact structures are provided in nanosheet devices, vertical FETs, and FinFETs. Such contact structures are obtained by delivering dopants to source/drain regions using a highly conformal, doped metal layer. The conformal, doped metal layer may be formed by ALD or CVD using a titanium tetraiodide precursor. Dopants within the conformal, doped metal layer are delivered during the formation of wrap-around metal silicide or metal germano-silicide regions. Dopant segregation at silicide/silicon interfaces or germano-silicide/silicon interfaces reduces contact resistance in the wrap-around contact structures. A contact metal layer electrically communicates with the wrap-around contact structures.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Adra V. Carr, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10347411
    Abstract: Embodiments of the invention are directed to a method of fabricating a yoke arrangement of an inductor. A non-limiting example method includes forming a dielectric layer across from a major surface of a substrate. The method further includes configuring the dielectric layer such that it imparts a predetermined dielectric layer compressive stress on the substrate. A magnetic stack is formed on an opposite side of the dielectric layer from the substrate, wherein the magnetic stack includes one or more magnetic layers alternating with one or more insulating layers. The method further includes configuring the magnetic stack such that it imparts a predetermined magnetic stack tensile stress on the dielectric layer, wherein a net effect of the predetermined dielectric layer compressive stress and the predetermined magnetic stack tensile stress on the substrate is insufficient to cause a portion of the major surface of the substrate to be substantially non-planar.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10109716
    Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vibhor Jain, Qizhi Liu, John J. Pekarik
  • Patent number: 10026839
    Abstract: A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj Mehrotra
  • Patent number: 9935107
    Abstract: Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M Cea, Roza Kotlyar, Harold W Kennel, Kelin J Kuhn, Tahir Ghani
  • Patent number: 9917019
    Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg
  • Patent number: 9892975
    Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming strained <100> n-channel field effect transistor (NFET) fins and adjacent strained <110> p-channel field effect transistor (PFET) fins on the same substrate. A <110> crystalline oxide layer may be either bonded or epitaxially grown on a substrate layer. A first SOI layer with a <100> crystallographic orientation and tensile strain may be bonded to the crystalline oxide layer. A second SOI layer with a <110> crystallographic orientation and compressive strain may be epitaxially grown on the crystalline oxide layer. The first SOI layer may be used to form the fins of a NFET device. The second SOI layer may be used to form the fins of a PFET device.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9865684
    Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Van Le, Robert Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy Zelick
  • Patent number: 9818868
    Abstract: A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz
  • Patent number: 9768262
    Abstract: Carbon-doped germanium stressor regions are formed in an nFET device region of a germanium substrate and at a footprint of a functional gate structure. The carbon-doped germanium stressor regions are formed by an epitaxial growth process utilizing monomethylgermane (GeH3—CH3) as the carbon source. The carbon-doped germanium stressor regions that are provided yield more strain in less volume since a carbon atom is much smaller than a silicon atom.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey L. Dittmar, Keith E. Fogel, Sebastian Naczas, Alexander Reznicek, Devendra K. Sadana
  • Patent number: 9666487
    Abstract: A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 9583507
    Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming strained <100> n-channel field effect transistor (NFET) fins and adjacent strained <110> p-channel field effect transistor (PFET) fins on the same substrate. A <110> crystalline oxide layer may be either bonded or epitaxially grown on a substrate layer. A first SOI layer with a <100> crystallographic orientation and tensile strain may be bonded to the crystalline oxide layer. A second SOI layer with a <110> crystallographic orientation and compressive strain may be epitaxially grown on the crystalline oxide layer. The first SOI layer may be used to form the fins of a NFET device. The second SOI layer may be used to form the fins of a PFET device.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9543388
    Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gen P. Lauer, Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight
  • Patent number: 9508832
    Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Jung Lee, Bonyoung Koo, Sunjung Kim, Jongryeol Yoo, Seung Hun Lee, Poren Tang
  • Patent number: 9472552
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ding-Yuan Chen, Chen-Hua Yu
  • Patent number: 9466670
    Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9431486
    Abstract: A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-cheon Seo, Charan Veera Venkata Satya Surisetty
  • Patent number: 9373638
    Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gen P. Lauer, Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight
  • Patent number: 9285417
    Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel J. Poindexter, James M. Crafts, Karre M. Greene, Kenneth A. Lavallee, Keith C. Stevens
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8981490
    Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8975142
    Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Abhijeet Paul, Abner Bello, Vimal K. Kamineni, Derya Deniz
  • Patent number: 8969969
    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan, Roger Allen Booth, Jr.
  • Patent number: 8962447
    Abstract: According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8927361
    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger Allen Booth, Jr., Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan
  • Patent number: 8916937
    Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 23, 2014
    Assignee: SuVOLTA, Inc.
    Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
  • Patent number: 8912568
    Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Huanxin Liu, Huojin Tu
  • Patent number: 8901662
    Abstract: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Baewon Yang
  • Patent number: 8895381
    Abstract: A method of forming a semiconductor device that includes providing a substrate including a biaxial strained semiconductor layer that is present directly on a dielectric layer, and patterning the biaxial strained semiconductor layer to provide a first conductivity region of a laterally relaxed semiconductor portion and a second conductivity region of a biaxial strained semiconductor portion, wherein the laterally relaxed semiconductor portion is present over an undercut region in the dielectric layer. A hydrogen anneal is applied to the first and second conductivity region, wherein the laterally relaxed semiconductor portion is relaxed to an unstrained state. A first semiconductor device is formed in first conductivity region and a second semiconductor device is formed in the second conductivity region.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8877579
    Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-kyun Song, Ha-jin Lim, Moon-han Park, Jin-ho Do
  • Patent number: 8847315
    Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Xia Li, Jun Yuan
  • Patent number: 8835994
    Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8815660
    Abstract: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qingqing Liang, Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8796802
    Abstract: Semiconductor photodetectors are provided that may enable optimized usage of an active detector array. The semiconductor photodetectors may have a structure that can be produced and/or configured as simply as possible. A radiation detector system is also provided.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 5, 2014
    Assignee: First Sensor AG
    Inventors: Michael Pierschel, Frank Kudella
  • Patent number: 8778752
    Abstract: A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: July 15, 2014
    Assignee: Fujitu Semiconductor Limited
    Inventor: Yasunobu Torii
  • Patent number: 8766371
    Abstract: There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 1, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 8748281
    Abstract: When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Thilo Scheiper, Uwe Griebenow
  • Patent number: 8723237
    Abstract: A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yasunobu Torii
  • Patent number: 8703620
    Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: April 22, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Joanna Wasyluk, Stephan Kronholz, Berthold Reimer, Sven Metzger, Gregory Nowling, John Foster, Paul Besser
  • Publication number: 20140091361
    Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
  • Patent number: 8664073
    Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
  • Patent number: 8658543
    Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: February 25, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Joanna Wasyluk, Stephan Kronholz, Yew-Tuck Chow, Richard J. Carter, Berthold Reimer, Kai Tern Sih
  • Patent number: 8658506
    Abstract: Methods and apparatus for selectively improving integrated circuit performance are provided. In an example, a method is provided that includes defining a critical portion of an integrated circuit layout that determines the speed of an integrated circuit, identifying at least a part of the critical portion that includes at least one of a halo, lightly doped drain (LDD), and source drain extension (SDE) implant region, and performing a speed push flow process to increase performance of the part of the critical portion that includes the at least one of the halo, the LDD, and the SDE implant region. The resultant integrated circuit can be integrated with a mobile device.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Choh fei Yeap, Ping Liu
  • Patent number: 8653604
    Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 18, 2014
    Assignee: SuVolta, Inc.
    Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
  • Patent number: 8647939
    Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Patent number: 8647951
    Abstract: Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e10 ions/cm2.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: February 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel