Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.

Abstract: A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.

Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.

Abstract: The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract: Provided is a method for manufacturing a MOS transistor.

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

Abstract: CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

Abstract: To provide a semiconductor device in which resistance of a source region and a drain region of a thin film transistor is reduced and a short channel effect is suppressed, and a manufacturing method thereof. The semiconductor device includes a gate electrode which is formed over a first semiconductor layer with a gate insulating film interposed therebetween; sidewalls which are formed on side surfaces of the gate electrode; and second semiconductor layers which are in contact with and stacked over end portions of the sidewalls and the first semiconductor layer, wherein the second semiconductor layers cover at least a part of the end portions of the sidewalls.

Abstract: The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of first semiconductor devices and a second plurality of semiconductor devices is provided, in which each of the first semiconductor devices are separated by a first pitch and each of the second semiconductor devices are separated by a second pitch. The first pitch separating the first semiconductor devices is less than the second pitch separating the second semiconductor devices. A low-k dielectric spacer is formed adjacent to gate structures of the first semiconductor devices. A stress inducing liner is formed on the second semiconductor devices.

Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

Abstract: An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate (103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104), an extended drain (106) implanted in a surface portion of the substrate (101) adjacent the second side wall (105) of the gate (103), a spacer (107) on the second side wall (105) of the gate (103), a source (108) implanted in a surface portion of the substrate (101) adjacent the first side wall (104) of the gate (103), and a drain (109) implanted in a surface portion of the substrate (101) adjacent the spacer (107) in such a manner that the extended drain (106) is arranged between the gate (103) and the drain (109).

Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

Abstract: The semiconductor device includes an n-channel transistor including n-type source/drain regions and a first gate electrode, a first sidewall insulating film formed on a side wall of the first gate electrode and having a Young's modulus smaller than a Young's modulus of silicon, a p-channel transistor including p-type source/drain regions and a second gate electrode, a second sidewall insulating film formed on a side wall of the second gate electrode and having a Young's modulus larger than the Young's modulus of silicon, a tensile stressor film formed, covering the n-channel transistor, and a compressive stressor film formed, covering the p-channel transistor.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: A method of forming sidewall spacers for a gate in a semiconductor device includes depositing a gate oxide layer over a gate and source/drain regions, and using a thermal anneal to oxidize silicon of the substrate and silicon of the gate after formation of the deposited oxide layer. A sidewall layer is deposited over the oxide layer following the oxidation, and the sidewall layer and oxide layer are patterned to form the sidewall spacers.

Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

Abstract: A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

Abstract: In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.

Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.

Abstract: A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall.

Abstract: According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process.

Abstract: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.

Abstract: A semiconductor device according to the present invention includes: a semiconductor layer; an element separating portion, formed in a top layer portion of the semiconductor layer and separating, in the semiconductor layer, a first element forming region for forming a first conductive type MOSFET and a second element forming region for forming a second conductive type MOSFET; a first gate insulating film, selectively formed on a top surface of the semiconductor layer in the first element forming region; a first gate electrode, formed on the first gate insulating film; a first sidewall, formed at a periphery of the first gate insulating film and the first gate electrode; a second gate insulating film, selectively formed on a top surface of the semiconductor layer in the second element forming region; a second gate electrode, formed on the second gate insulating film; and a second sidewall, formed at a periphery of the second gate insulating film and the second gate electrode.

Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.

Abstract: The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of first semiconductor devices and a second plurality of semiconductor devices is provided, in which each of the first semiconductor devices are separated by a first pitch and each of the second semiconductor devices are separated by a second pitch. The first pitch separating the first semiconductor devices is less than the second pitch separating the second semiconductor devices. A low-k dielectric spacer is formed adjacent to gate structures of the first semiconductor devices. A stress inducing liner is formed on the second semiconductor devices.

Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

Abstract: A method for manufacturing at least one structure for a double grid field effect transistor, including: forming, on an isolating face of a first substrate, a stack comprising successively at least one layer of rear grid material, a layer of rear grid isolator, one semi-conducting zone for each structure to be manufactured, an electrically insulating layer of a front grid, at least one layer of front grid material and a masking element for each structure to be manufactured, placed facing the semi-conducting zone; forming in the at least one layer of front grid material a pattern reproducing a shape of the masking element and comprising etching of the layer of front grid material to eliminate the front grid material outside the pattern; and forming on free faces of the pattern a sacrificial spacer covering a first part of the semi-conducting zone.

Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.

Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Abstract: A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region.

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract: A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.

Abstract: A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.

Abstract: By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

Abstract: A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.