Characterized By Bent Parts (epo) Patents (Class 257/E23.047)
  • Patent number: 7525183
    Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: April 28, 2009
    Assignee: General Semiconductor, Inc.
    Inventors: Paddy O'Shea, Eamonn Medley, Finbarr O'Donoghue, Gary Horsman
  • Patent number: 7508054
    Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: March 24, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
  • Patent number: 7504714
    Abstract: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: March 17, 2009
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventor: Geng-Shin Shen
  • Patent number: 7485973
    Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip, a solder ball for external connection, wiring for electrically connecting the semiconductor chip and the solder ball, a stress relieving layer provided on the semiconductor chip, and a stress transmission portion for transmitting stress from the solder ball to the stress relieving layer in a peripheral position of an electrical connection portion of the solder ball and wiring.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: February 3, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7476913
    Abstract: A light emitting device has a cup portion with a bottom surface opening, and one electrode of a light emitting element is connected to the cup portion. The other electrode of the light emitting element is connected to a lead set up from an inner space to outside the cup portion using the opening of the cup portion. Each electrode and lead of the light emitting device can be electrically connected without bonding wires. This prevents shadows or light unevenness from reflecting the shape of the bonding wire, thereby enhancing light-emission efficiency. As an alternative to setting up the lead from inside to the outside of the cup portion, the lead existing outside the cup portion and the other electrode are electrically connected via the bonding wire through the cup portion's opening. Thus, light outputted outside of the light emitting device is not intercepted by the bonding wire.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 13, 2009
    Assignees: Renesas Technology Corp., Hitachi Cable Precision Co., Ltd., Hitachi Cable, Ltd.
    Inventors: Hiroyuki Isobe, Gen Murakami, Toshikatsu Hiroe
  • Patent number: 7462932
    Abstract: A wafer or a portion of a wafer including capped chips such as surface acoustic wave (SAW) chips is provided with terminals by applying a terminal-bearing element such as a dielectric element with terminals and leads thereon, or a lead frame, so that the terminal-bearing element covers the caps, and the leads are aligned with channels or other depressions between the caps. The leads are connected to contacts on the wafer, and the wafer is severed to form individual units, each including terminals supported by the cap and connected to the contacts by the leads. The resulting units can be handled and processed in the same manner as ordinary chips or chip assemblies.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: December 9, 2008
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Yoichi Kubota
  • Publication number: 20080251902
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Application
    Filed: June 17, 2008
    Publication date: October 16, 2008
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7425755
    Abstract: A semiconductor package mainly includes a semiconductor chip and a plurality of leads at the periphery of the semiconductor chip. Each of the leads has a first portion, a second portion and opposing upper and lower surfaces, wherein the second portion of the leads are bent upwards. The semiconductor package has a plurality of bonding wires with one ends connected to the bonding pads of the semiconductor chip and the other ends connected to the first portions of the leads. The semiconductor package is provided with a package body formed over the semiconductor chip and the leads, wherein each of the leads is substantially embedded in the package body with the lower surface thereof exposed from the package body. The present invention further provides a method for manufacturing the semiconductor package.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: September 16, 2008
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Sheng Tsung Liu
  • Patent number: 7361531
    Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: April 22, 2008
    Assignee: Allegro Microsystems, Inc.
    Inventors: Nirmal Sharma, Virgil Ararao
  • Patent number: 7345356
    Abstract: Packages for an optical integrated circuit die and a method for making such packages are disclosed. The package includes a die, a die pad, a plurality of lead fingers, and an encapsulating dielectric material. The downward second pad surface of the die pad bearing an integrated circuit is encapsulated by a bottom encapsulating dielectric material. The top encapsulating dielectric material provides the function for protecting the leadframe from severe environment. The top encapsulating dielectric material can be neglected if there is no threat on the integrated circuit die and the leadframe. Multiple of lead fingers are mounted on the printed circuit board. A portion of the printed circuit board is removed in order to provide an optical path for the light beam transmitted from a light source through the transparent bottom encapsulating dielectric material into the integrated circuit die. The method of making a package includes forming a leadframe including a die pad and a plurality of lead fingers.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: March 18, 2008
    Assignee: Capella Microsystems Corp.
    Inventor: Chih-Cheng Chien
  • Patent number: 7332806
    Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: February 19, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Chung-Lin Wu
  • Publication number: 20070290325
    Abstract: A surface mounting structure and a packaging method thereof comprises a chip, a first conducting wire and a second conducting wire. The two conducting wires instead of lead frame architecture of the prior art is that the lead frame and a bridge jumper connected with N junction and P junction instead of the two conducting wires. The two conducting wires are drawn out from a bottom of a package, and are pressed and bent to original surface of the surface mounting pins so as to increase space utilization rate. Thereby it is to improve a complicated lead frame architecture of the prior art, increase use space and simplify system design.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventors: Kuo-Liang Wu, Kuo-Shu Iu, Chih-Wei Chang
  • Publication number: 20070284709
    Abstract: A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and a second leadframe connected to the first surface.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 13, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Bernhard P. Lange
  • Patent number: 7307351
    Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 11, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7298025
    Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: November 20, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7279784
    Abstract: A semiconductor package mainly includes a semiconductor chip and a plurality of L-shaped leads arranged at the periphery of the semiconductor chip. Each of the L-shaped leads has an inner lead portion exposed out of the lower surface of the semiconductor package and an outer lead portion formed substantially parallel to and adjacent to one of the side surfaces of the semiconductor package. The semiconductor chip has a plurality of bonding pads electrically coupled to the inner lead portions of the L-shaped leads. The semiconductor package is provided with a package body formed over the semiconductor chip and the inner lead portions of the L-shaped leads.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: October 9, 2007
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Sheng Tsung Liu
  • Patent number: 7256482
    Abstract: An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: August 14, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Alfred Kummerl, Anthony L. Coyle, Bernhard Lange
  • Patent number: 7242077
    Abstract: A leadframe includes a die pad, a plurality of tie bars, a plurality of metal extrusions and a plurality of leads. The leads are arranged around the die pad. The tie bars are connected to the corners of the die pad, and the metal extrusions are connected to the sides of the die pad but separated from the tie bars. Each metal extrusion has a locking hole and a bonding surface, which is higher than the die pad. The metal extrusions are configured for improving ground connections by wire-bonding. When a bottom surface of the die pad is exposed from an encapsulant for a semiconductor package, the metal extrusions help to secure the die pad without stress transmission.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: July 10, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kang-Wei Ma, Shu-Chen Yang, Ying-Chen Sun, Li-Ping Chen
  • Patent number: 7239008
    Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: July 3, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 7235881
    Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 26, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20070057360
    Abstract: Semiconductor package films and a display module comprising a packaged semiconductor device punched from a semiconductor package film are provided. In one embodiment, the invention provides a semiconductor package film comprising a base film comprising a plurality of semiconductor device regions, an intermediate region disposed on a first surface of the base film and disposed between two semiconductor device regions, and a reinforcing member attached to a second surface of the base film opposite the first surface of the base film and attached opposite the intermediate region. Each semiconductor device region comprises a semiconductor mounting region adapted to receive a semiconductor chip, and first and second metal line regions.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 15, 2007
    Inventors: Si-hoon Lee, Jae-cheon Doh, Sa-yoon Kang
  • Publication number: 20070012947
    Abstract: A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first major electrode of the die. The thin metal clip has a relatively large surface area, and package resistance which is caused by skin effect phenomenon is reduced thereby in high frequency applications.
    Type: Application
    Filed: September 19, 2006
    Publication date: January 18, 2007
    Inventor: John Larking
  • Publication number: 20060267189
    Abstract: A circuit device of the present invention includes a first element which is placed parallel to a first reference plane and which senses a physical quantity, and a second element placed parallel to a second reference plane which intersects the first reference plane at a predetermined angle. The circuit device further includes a sealing resin for integrally sealing the first and second elements, a first conductive pattern which is electrically connected to the first element and placed parallel to the first reference plane and which has a back surface exposed from the sealing resin, and a second conductive pattern which is electrically connected to the second element and placed parallel to the second reference plane and which has a back surface exposed from the sealing resin.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 30, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Patent number: 7138707
    Abstract: A semiconductor package comprising a semiconductor die which has opposed first and second surfaces and at least first and second bond pads disposed on the second surface thereof. In addition to the semiconductor die, the semiconductor package includes at least one lead having opposed first and second surfaces, the first surface of the lead being electrically connected to the first bond pad. Also included in the semiconductor package is at least one conductive post having opposed first and second surfaces, the first surface of the conductive post being electrically connected to the second bond pad. A package body at least partially encapsulates the semiconductor die, the lead, and the conductive post such that the second surface of the lead and the second surface of the conductive post are exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: November 21, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Seung Ju Lee, Won Chul Do, Kwang Eung Lee
  • Publication number: 20060197187
    Abstract: The semiconductor device includes a semiconductor body having a first and an opposite second main surface and side faces connecting the main surfaces, a circuit region in the semiconductor body adjacent to the first main surface, having a circuit contact terminal, a metallization region extending from the circuit contact terminal on the first main surface onto a side face of the semiconductor body to provide an exposed contacting region on the side face of the semiconductor body, and an insulation layer arranged between the metallization region and the semiconductor body, the insulation layer having an opening for electrically connecting the circuit contact terminal to the metallization region.
    Type: Application
    Filed: January 27, 2006
    Publication date: September 7, 2006
    Applicant: Infineon Technologies AG
    Inventors: Gerhard Lohninger, Ulrich Krumbein
  • Publication number: 20060186516
    Abstract: A semiconductor device including a semiconductor chip having first and second principal surfaces is disclosed. The semiconductor chip includes a first electrode formed on the first principal surface and a second electrode formed on the second principal surface. A first lead frame includes a first connecting portion connected to the first electrode and a first terminal portion. A second lead frame includes a second connecting portion connected to the second electrode and a second terminal portion. The semiconductor chip is sealed by a housing. The housing is formed so as not to cover part of surfaces of the first and second connecting portions.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 24, 2006
    Inventor: Satoshi Yanagisawa