Abstract: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant.

Abstract: A curable composition, suitable for underfill encapsulant, has two distinct phase domains after cure, a continuous phase and a discontinuous phase, in which one phase has a modulus value of 2 GPa or greater, and the second phase has a modulus value at least 1 Gpa less than the first phase, characterized in that the phases are generated in situ as the composition cures.

Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Abstract: A positive tone photosensitive composition comprising: (A) an alkali-soluble resin having a phenolic hydroxyl group; (B) a phenol resin modified by a compound having an unsaturated hydrocarbon group containing 4 to 100 carbon atoms; (C) a compound that generates an acid by the action of light; (D) a thermal cross-linker that crosslinks the ingredient (A) and the ingredient (B) by heating; and (E) a solvent.

Abstract: A method of manufacture of a semiconductor packaging system includes: providing a base substrate having edges; mounting an electrical interconnect on the base substrate; and applying an encapsulant having a reference marker and an opening over the electrical interconnect, the reference marker around the electrical interconnect based on physical locations of the edges.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit on the carrier; mounting a z-interconnect on the carrier, the z-interconnect for supporting a trace cantilevered over the integrated circuit; encapsulating the integrated circuit with an encapsulation; removing the carrier; and depositing a substrate below the integrated circuit.

Abstract: The invention relates to an organic optoelectronic device, such as a display, lighting or signalling device, that is protected from the ambient air by a sealed encapsulation in the form of a thin film, and to a method for encapsulating such a device. An optoelectronic device (1) according to the invention is coated with a sealed multi-layer encapsulation structure (20) comprising alternating inorganic layers (21a to 26a) and organic layers (21b to 25b). According to the invention, the device is such that at least one of said organic layers consists of a crosslinked adhesive film (21b to 25b) based on a glue that can be crosslinked thermally or by electromagnetic radiation, the or each adhesive film having a thickness uniformly lower than 200 n, said thickness being obtained by passing the film, which is deposited and not yet cross-linked, through a vacuum, such that the total thickness of the encapsulation structure is minimised.

Abstract: A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

Abstract: A system in a package comprising a flip chip semiconductor die on a package substrate, a spacer on the package substrate, and a wire bond semiconductor die supported by the spacer and the flip chip semiconductor die.

Abstract: Metal particles are applied to a metal foil. A semiconductor chip is placed over the metal foil with contact elements of the semiconductor chip facing the metal particles. The metal particles are heated and the metal foil is structured after heating the metal particles.

Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.

Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Abstract: A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillars; depositing a first protective film on the sidewalls of the pillar; first etching the semiconductor substrate with the pillar deposited with the first protective film as a mask; forming a first insulating film on the sidewalls of the pillar and the first etched semiconductor substrate; second etching the semiconductor substrate with the pillar including the first insulating film as a mask; forming a second protective film and a second insulating film on the surface of the second etched semiconductor substrate; depositing a barrier film on the sidewalls of the pillar including the second insulating film; and removing the first insulating film, the second insulating film and the barrier film disposed at one sidewall of the pillar to form a contact hole defined by the first protective film and the second protective film.

Abstract: Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO2—SiGe anchor area determines the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

Abstract: A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is coupled to the via and encapsulated. Then, at least a part of the baseplate is removed. An integrated circuit package is produced by the method.

Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack.

Abstract: An integrated circuit package system is provided including forming an integrated circuit die, forming an interference-fit feature in the integrated circuit die, fitting a support element within the interference-fit feature, connecting an external interconnect and the integrated circuit die, and encapsulating the integrated circuit die.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: A microelectronic package comprises a die (110) having a front side (111) containing active circuitry (115) and a back side (112) opposite the front side and a film (120) on the back side of the die. The film has a thickness (121) of at least 20 micrometers, a Young's modulus of at least 10 GPa, and a post-cure glass transition temperature of at least 100° Celsius.

Abstract: An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die.

Abstract: An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads.

Abstract: A semiconductor device of the present invention (1) has a substrate (2); a semiconductor element (3) provided on at least one side of the substrate (2); a first resin (4) obtained by curing a first resin composition which fills a gap between the substrate (2) and the semiconductor element (3); and a second resin (5) which covers the substrate (2) and the first resin (4), and obtained by curing a second resin composition after the first resin composition is cured. In the present invention, adhesion strength between the first resin (4) and the second resin (5) is 18 MPa or larger at room temperature.

Abstract: The present invention provides a silicone resin composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two hydrogen atoms each bonded to a silicon atom, (C) a catalyst comprising a platinum group metal, (D) fine silicone particles, and (E) a (meth)acrylate compound. The present silicone resin composition cures in a short time to form a cured product having excellent adhesion strength with solder resists and copper substrates.

Abstract: Electronic device packages with electromagnetic compatibility (EMC) coating thereon are presented. An electronic device package includes a chip scale package having a CMOS image sensor (CIS) array chip and a set of lenses configured with an aperture. An encapsulation is molded overlying the chip scale package. A shield is atop the encapsulation. A frame fixes the set of lenses to the encapsulation. An electromagnetic compatibility (EMC) coating is formed on the encapsulation to prevent electromagnetic interference.

Abstract: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such a way that the sensor region faces the opening. The sensor chip is embedded into a rubber-elastic composition on all sides in the interior of the housing. The sensor housing has a sandwich-like framework having three regions arranged one above another, including an intermediate region with the rubber-elastic composition.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material.

Abstract: A resin composition containing a silica-based filler which differs in refractive index by ±0.03 from the curable base resin and has a thermal conductivity no lower than 0.5 W/m·K, and a light-emitting diode encapsulated with said resin composition. The resin composition is preferably prepared from a curable silicone resin which imparts a cured product having a refractive index of 1.45 to 1.55 and cristobalite powder dispersed therein.

Abstract: A manufacturing method for a packaging structure of SIP (system in package) includes the following steps. First step is providing a substrate having electronic devices thereon. Second step is covering the electronic devices by a mixture of a molding compound and a conductive polymer precursor so as to form a molding structure, wherein the substrate, the electronic devices and the molding structure forms a collective electronic module. Third step is separating the collective electronic module into a plurality of individual electronic modules. Fourth step is performing a doping step by using a doping element for transforming the conductive polymer precursor in the mixture into a conductive layer near the surface of the molding structure. Therefore, the manufacturing method is optimized for forming a shielding structure of the SIP module.

Abstract: The present invention relates to thermosetting resin compositions that include maleimide-, nadimide- or itaconimide-containing compounds and a metal/carboxylate complex and a peroxide, which is curable at a low temperature at relative short period of time, such as less than about 100° C., for instance 55-70° C., over a period of time of about 30 to 90 minutes. The invention further provides methods of preparing such compositions, methods of applying such compositions to substrate surfaces, and packages and assemblies prepared therewith for connecting microelectronic circuitry.

Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface; (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward; (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip; and (d) polishing the encapsulation resin layer to expose a top surface of the pad.

Abstract: The present invention refers to a multilayer barrier film capable of encapsulating a moisture and/or oxygen sensitive electronic or optoelectronic device, the barrier film comprises at least one nanostructured layer comprising reactive nanoparticles capable of interacting with moisture and/or oxygen, the reactive nanoparticles being distributed within a polymeric binder, and at least one ultraviolet light neutralizing layer comprising a material capable of absorbing ultraviolet light, thereby limiting the transmission of ultraviolet light through the barrier film

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas. The solder balls are disposed on the ball-placement areas.

Abstract: A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices.

Abstract: A method for producing an electronic component comprising barrier layers for the encapsulation of the component comprises, in particular, the following steps: providing a substrate (1) with at least one functional layer (22), applying at least one first barrier layer (3) on the functional layer (22) by means of plasma-enhanced atomic layer deposition (PEALD), and applying at least one second barrier layer (4) on the functional layer (22) by means of plasma-enhanced chemical vapor deposition (PECVD).

Abstract: An improved semiconductor package includes thermal tape placed over a top side of a die that is attached to a substrate with an underfill material. The tape extends to the substrate. The tape deforms with heat and entraps the die and underfill material. Air bubbles are trapped between the tape and the die and underfill material. The tape can be weighted and lined with an adhesive material. The tape aids in preventing the die from cracking due to mishandling.

Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

Abstract: An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.

Abstract: A semiconductor chip package is provided. A semiconductor chip package includes a base comprising a top surface and a bottom surface, the top surface comprising a die attach region and a through-hole forming region surrounding the die attach region, a die attached on the die attach region, a molding material encapsulating the die and a plurality of through holes filled up with the molding material formed in the through-hole forming region.

Abstract: A packaging system for preventing underfill overflow includes a package substrate having a solder mask a die attach site, a solder mask dam on the solder mask proximal to the die attach site, and a trench in the solder mask proximal to the die attach site. The trench and the solder mask dam are adapted to constrain flow of an underfill material.

Abstract: An electronic circuit includes at least two organic components interconnected by conductor tracks and having a common carrier substrate. The components and the conductor tracks are formed from layer portions. An uppermost layer portion, remote from the carrier substrate, of the electronic circuit is of a patterned configuration comprising an electrically conducting material. The patterned uppermost layer portion on its side remote from the carrier substrate is provided with at least one protective layer arranged in congruent relationship with the uppermost layer portion. The at least two organic components include at least one first component of a first component type and at least one second component of a second component type different therefrom. Components of the same component type are respectively protected by a protective layer of the same composition and/or the same structure corresponding to that component type and differing from one another according to the corresponding component type.

Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.

Abstract: A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face.

Abstract: A semiconductor chip grid array package includes a die attach pad and a plurality of connector pads. A semiconductor die is mounted on the die attach pad, the semiconductor die having external connection terminals electrically connected respectively to the connector pads. An encapsulating material encapsulates the die and connector pads. A stud protrudes from each of the connector pads for providing an external electrical contact for the semiconductor chip grid array package. Each of the connector pads and respective studs are formed from an electrically conductive sheet. The connector pads have a thickness of at least 60% of the thickness of the conductive sheet and the respective studs have a thickness of no more than 40% of the thickness of the conductive sheet.

Abstract: Provided are a semiconductor package and a method of forming the same. The semiconductor package includes a stress reliever disposed on a part (more specifically, a weak part) of a semiconductor chip. The stress reliever relieves thermal and/or physical stresses caused by a molding layer. As a result, the semiconductor chip does not suffer from the thermal and/or physical stresses.

Abstract: The present invention relates to a method for encapsulating a substrate, which comprises: (a1) providing a substrate with a plurality of chips mounted on a top of the substrate; (b1) compressing a dry film photoresist on the top side of the substrate to form a photoresist layer; (c1) exposing the photoresist layer to a light source through a mask to form unexposed photoresist regions and exposed photoresist regions; (d1) developing the photoresist layer to uncover underlying portions of the unexposed photoresist regions; (e1) molding the top side of the substrate with a molding material; (f1) curing the molding material; and (g1) removing the unexposed photoresist regions from the substrate with a photoresist-removing agent.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.