Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a packaging substrate, a chip, an interposer substrate, a wire and an adhesive layer. The packaging substrate has an upper packaging surface. The chip is disposed on the upper packaging surface. The wire connects the packaging substrate and the interposer substrate. The adhesive layer is disposed between the packaging substrate and the interposer substrate, and covers the entire chip and part of the upper packaging surface. The adhesive layer includes a first adhesive part and a second adhesive part. The first adhesive part adheres the interposer substrate and the chip. The second adhesive part surrounds the first adhesive part, adheres the interposer substrate and the packaging substrate, and supports a periphery of the interposer substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: attaching an integrated circuit having a through via over a substrate with the through via coupled to the substrate; attaching a conductive support over the substrate and adjacent to the integrated circuit; forming an encapsulation over the substrate with the conductive support exposed from the encapsulation; and attaching an external interconnect under the substrate.

Abstract: It is described a procedure for the integration of semiconductor incompatible materials in a process family created for the production of passive electric components and active electric components formed within integrated circuits. The procedure is applicable in known techniques like bipolar, MOS or BIMOS processes for semiconductor production. The modular concept of the described procedure may combine diodes, resistors and capacitors, which components are made from different materials. The provision of an encapsulation material for a semiconductor incompatible material enables the manufacturing of integrated circuits even within a sensitive environment with respect to contaminations originating from the semiconductor incompatible material. The encapsulation is provided early within the manufacturing process such that the risk for a contamination may be reduced to a minimum.

Abstract: The invention provides advances in the arts with useful and novel integrated packaging having passive components included within packages also containing one or more ICs. The integrated passive components may include inductors, transformers, and capacitors, and are preferably constructed of leadframe materials. Typically, one or more magnetic field storage body is used in forming the coils in order to enhance the electrical performance characteristics of the passive component.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular, concentric grooves (163). Each groove is cooperatively enclosed by a first groove wall (165) and a second groove wall (166). The first groove wall is a portion of a circumferential side surface of a cone, and a conical tip of the cone is located on the light emitting surface of the LED chip.

Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.

Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable silicone composition which is fed into the space between the mold and the unsealed semiconductor device to compression molding, the method being characterized by the fact that the aforementioned curable silicone composition comprises at least the following components: (A) an epoxy-containing silicone and (B) a curing agent for an epoxy resin; can reduce warping of the semiconductor chips and circuit board, and improve surface resistance to scratching.

Abstract: Method for increasing the moisture-proof capability of a chip includes coating moisture-proof glue at the chink of the chip. More particularly, when the packaging structure carries a chink exposed to outside of the chip, the chink is coated with the moisture-proof glue for preventing moisture from entering the internal part of the chip so as to increase the moisture-proof capability of the chip.

Abstract: The present invention provides a resin sheet for encapsulating an optical semiconductor element, the resin sheet containing an encapsulation resin layer, an adhesive resin layer, a metal layer and a protective resin layer, in which the encapsulation resin layer and the metal layer adhered onto the adhesive resin layer are disposed adjacently to each other, the protective resin layer is laminated on the encapsulation resin layer and the metal layer so as to cover both the encapsulation resin layer and the metal layer, and the encapsulation resin layer has a taper shape expanding toward the protective resin layer; and an optical semiconductor device containing an optical semiconductor element encapsulated by using the resin sheet. The optical semiconductor element encapsulation resin sheet of the invention can be suitably used for back lights of liquid crystal screens, traffic signals, large-sized outdoor displays, billboards and the like.

Abstract: A module substrate has an interconnection electrode that is exposed at a side end face thereof. A semiconductor component including an IC chip is mounted on the module substrate. A molded part comprising a resin is formed so as to cover at least a part of the semiconductor component. A coating with higher heat conductivity than the molded part is formed on the surface of the molded part by applying a paste made of material with higher heat conductivity than the molded part. This improves heat dissipation. The coating can be formed such that it extends to the surface of the main substrate on which the module substrate with the semiconductor component is mounted and comes into contact with the interconnection electrode on the surface of the main substrate. This further improves heat dissipation.

Abstract: Present embodiments are directed to an adhesive and method for assembling a chip package. The adhesive may be used to couple a chip to a substrate, and the adhesive may include an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator.

Abstract: The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

Abstract: Packaging systems and methods of manufacture are provided. In this regard, a representative system comprises a first layer of liquid crystal polymer (LCP), a first electronic component supported by the first layer, and a second layer of LCP. The first layer and the second layer encase the first electronic component.

Abstract: In a method of manufacturing a semiconductor package, a chip is disposed on a carrier. An inert gas is run around one end of a line portion of a copper bonding wire while the end is being formed into a spherical portion. The spherical portion is bonded to a pad of the chip. The chip and the copper bonding wire are sealed and the carrier is covered by a molding compound.

Abstract: A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.

Abstract: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.

Abstract: A positive photosensitive resin composition for spray coating of the present invention is used for forming a coating film onto a substrate such as a semiconductor element mounting substrate, a ceramics substrate or an aluminium substrate by spray coating. The positive photosensitive resin composition is characterized by containing (A) an alkali soluble resin, (B) a compound which generates an acid by the action of light and (C) a solvent, and having a viscosity of 2 to 200 cP.

Abstract: This semiconductor device is a semiconductor device in which a semiconductor element is flip-chip mounted onto a circuit substrate and the semiconductor element is covered and sealed with a sealing resin. A recess portion is formed in the sealing resin on a surface opposite to the mounting surface of the semiconductor element. Warping of the semiconductor device is reduced by the action of this recess portion.

Abstract: A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface.

Abstract: A semiconductor device includes a semiconductor chip, and an encapsulation resin which covers and encapsulates the semiconductor chip, the semiconductor chip having a recess formed in the surficial portion thereof; the recess having, on the deeper side than a predetermined portion thereof, a portion having a larger width than the predetermined portion has; and the encapsulation resin being anchored in the recess.

Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding use resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding use resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. In the semiconductor chip mounted structure formed in this way, entire side faces at the corner portions of the semiconductor chip are covered with the seal-bonding use resin.

Abstract: A semiconductor device 1 is equipped with a first substrate 3 on which a first semiconductor chip 2 is mounted, a second substrate 5 on which a second semiconductor chip 4 is mounted, and connecting sections 6 that electrically connect the first substrate 3 and the second substrate 5. The first substrate 3 has build-up layers 31A and 31B in each of which an insulating layer 311 containing a resin and conductor interconnect layers 312 and 313 are laminated alternately, and the respective conductor interconnect layers 312 are connected by a conductive layer 314 provided in via holes of the insulating layers 311. The second substrate 5 also has build-up layers 31A and 31B.

Abstract: A method of manufacturing a sensor node module includes forming a protruding structure on a carrier. A sensor die is applied onto the protruding structure with an active sensing surface of the sensor die facing the carrier. The sensor die is encapsulated with mold material, wherein the protruding structure prevents the mold material from covering the active sensing surface. The carrier and the protruding structure are removed from the sensor die.

Abstract: Differences in contraction forces of a sealing resin can be alleviated and strain on a package can be reduced even when electronic components are unevenly positioned on a substrate. An electronic device (100) includes a substrate 102, electronic components (104, 108) mounted on one face of the substrate 102, and a sealing resin 118 formed on the one face of the substrate 102 and which seals the electronic components. The sealing resin 118 includes a first resin region 120 made up of a first resin composition and a second resin region 122 made up of a second resin composition, and is formed so as to have, as seen in planar view, a region in which only the first resin region 120 exists and a region in which only the second resin region 122 exists.

Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

Abstract: A method of producing an electronic connection device, including: a) formation, in a plane of a support substrate, of at least one first contact element and, in a direction approximately perpendicular to the plane, of at least one second contact element having a first end in electrical contact with the first contact element or elements and a second end, the second contact element or elements including one or more metal tracks standing up along the direction perpendicular to the surface of the substrate; b) then positioning at least one electrical or electronic component in contact with the first contact element or elements; and c) encapsulation of the component(s) and of the first and second contact elements, at least the second end or ends of the second contact element or elements being flush with the surface of the encapsulating material.

Abstract: A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device includes a cavity housing and a sensor chip. In one embodiment, the cavity housing has an opening to the surroundings. The sensor region of the sensor chip faces said opening. The sensor chip is mechanically decoupled from the cavity housing. In one embodiment, the sensor chip is embedded into a rubber-elastic composition on all sides in the cavity of the cavity housing.

Abstract: The assembly (100) comprises a laterally limited semiconductor substrate region (15) in which an electrical element (20) is defined. Thereon, an interconnect structure (21) is present. This is provided, at its first side (101) with contact pads (25,26) for coupling to an electric device (30), and at its second side (102) with connections (20) to the electrical element (11). Terminals (52,53) are present at the second side (102) of the interconnect structure (21), and coupled to the interconnect structure (21) through extensions (22,23) that are laterally displaced and isolated from the semiconductor substrate region (15). An electric device (30) is assembled to the first side (101) of the interconnect structure (21), and an encapsulation (40) extending on the first side (101) of the interconnect structure (21) so as to support it and encapsulating the electric device (30) is present.

Abstract: A method of evaluating the flame retardancy of a sealing resin comprises a step of fusion cutting a heating element by causing the heating element to generate heat by the passage of electric current to a test sample of a molded body of the sealing resin including the heating element therein; a step of igniting the sealing resin by continuing the passage of electric current even after the heating element is fusion-cut; and a step of measuring voltage and/or current applied in a period from when the heating element is fusion-cut to the ignition of the sealing resin. The test sample is used in the method of evaluating the flame retardancy and provided with a heating wire; conducting terminals made of metal having an electric resistance lower than the heating wire and connected to both ends of the heating wire; and a sealing resin layer covering the outer periphery of the heating wire.

Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.

Abstract: Consistent with an example embodiment, there is a method for fabricating a semiconductor package having a substrate. The method comprises defining an encapsulation boundary on a surface of the substrate; the encapsulation boundary is divided into a molding region and a non-molding region. Over the substrate, a plurality of conductive traces is provided. Each conductive trace has an inner connection located in the molding region and an outer connection located in the non-molding region. A plurality of non-conducting dummy traces across the encapsulation boundary is provided. The plurality of non-conductive dummy traces are interposed among the conductive traces and are spaced apart at an interval less than a predetermined minimum air-vein forming distance (Dmln). A solder mask over the substrate covers the conductive traces and the non-conductive dummy traces. The molding region of the substrate is encapsulated with a molding compound.

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting a circuit assembly having an assembly end next to the connect contact and an edge pad over the stack board; connecting the edge pad with the stack board; and applying an edge encapsulant over the connect contact and over the assembly end with the edge encapsulant extending no more than half the width of the stack board.

Abstract: With a semiconductor apparatus package of example embodiments of the technology disclosed herein and a method of producing the semiconductor apparatus package, the semiconductor apparatus package includes a circuit board and a semiconductor device sealed with sealing resin. The circuit board has a groove in a section of a surface of the circuit board. The section is outside of the resin sealing section, and the surface includes the resin sealing section. The groove is at least partially filled with sealing resin having seeped from a resin sealing section. Thus, in the semiconductor apparatus package including the circuit board, which is exposed from the resin sealing section, and the semiconductor device sealed on the circuit board with the sealing resin, the spread of a thin resin film onto that exposed circuit board resulting from seepage of resin sealing the semiconductor device is prevented.

Abstract: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.

Abstract: The present invention relates to a thermosetting silicone resin composition including a condensation reactable substituent group-containing silicon compound and an addition reactable substituent group-containing silicon compound; a silicone resin; a silicone resin sheet obtained from the thermosetting silicone resin composition or the silicone resin, and a use thereof.

Abstract: A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads are formed; and a second surface opposite to the first surface, (b) connecting the pads to each other by conductive connectors; (c) sealing the first surface of the semiconductor wafer, the dicing grooves and the conductive connectors with a resin; (d) grinding the second surface of the semiconductor wafer, thereby forming a group of sealed chips; (e) dividing the group of sealed chips into individual sealed chips; (f) mounting and stacking the individual sealed chips on a wiring substrate having connection terminals thereon; and (g) electrically-connecting the conductive connectors and the connection terminals using a conductive member.

Abstract: An intermediate structure for semiconductor devices includes a wiring board, a plurality of semiconductor chips mounted on the wiring board, and a sealing body for collectively sealing the plurality of semiconductor chips and having a region with a different thickness.

Abstract: A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate and including a body, a self-adhesive protective layer, and a plurality of bumps protruding from the self-adhesive protective layer. The self-adhesive protective layer is formed on the chip but leaves the bumps exposed. The self-adhesive protective layer is made of a photosensitive adhesive, thermosetting adhesive, or dielectric material. The chip is coupled to the substrate via the self-adhesive protective layer, thus allowing the bumps to be electrically connected to the bonding fingers and at least an end of the opening to be exposed. The method enables a more streamlined manufacturing process and lower fabrication costs by dispensing with adhesive dispensing.

Abstract: A semiconductor device is made by forming a build-up interconnect structure over a substrate. A semiconductor die is mounted to the build-up interconnect structure. The semiconductor die is electrically connected to the build-up interconnect structure. A ground pad is formed on the build-up interconnect structure. An encapsulant is formed over the semiconductor die and build-up interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the build-up interconnect structure to isolate the semiconductor die from inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. The substrate is removed. A backside interconnect structure is formed over the build-up interconnect structure, opposite the semiconductor die.

Abstract: A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an inner stacking module die; encapsulating the inner stacking module die with an inner stacking module encapsulation to form an inner stacking module, the inner stacking module encapsulation having an inner stacking module protrusion having a planar protrusion surface; and encapsulating at least part of the inner stacking module encapsulation with an encapsulation having a flat top coplanar with the planar protrusion surface or fully encapsulating the inner stacking module encapsulation.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: A structure for protecting electronic package contacts is provided. The structure includes at least an electronic contact mounted on a chip, a dielectric layer, a conductor trace line and a protective layer. The protective layer is used to prevent stresses from being gathered within electronic contacts on the chip through surroundingly covering the conductor trace line.

Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.