Abstract: A thermosetting tape is adopted as a dicing tape and, after package dicing, the thermosetting tape is heated, then a desired one of divided CSPs is picked up by an inverting collet. Since the thermosetting tape is heated o a predetermined temperature so that its adhesive force becomes zero, the CSP can be picked up by the inverting collet without peeling it off from the thermosetting tape. Thus, peel-off charging does not occur and therefore it is not necessary to perform a destaticizing process. As a result, it is possible to improve the production efficiency in assembling the semiconductor device (CSP).

Abstract: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.

Abstract: In a circuit device of the present invention, the lower surface side of a circuit board and part of side surfaces thereof are covered with a second resin encapsulant, and the upper surface side and the like of the circuit board are covered with a first resin encapsulant. Since heat dissipation to the outside of the circuit device is achieved mainly through the second resin encapsulant, a particle size of filler contained in the second resin encapsulant is made larger than a particle size of filler contained in the first resin encapsulant. Heat dissipation to the outside of the circuit device is greatly improved.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole.

Abstract: An integrated package system with die and package combination includes forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit.

Abstract: With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process.

Abstract: The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Abstract: A method for manufacturing a light-emitting case includes forming a PLED (Polymer Light Emitting Diode) device, disposing the PLED device into a mold, and utilizing the mold to sheathe the PLED device with transparent plastic material in an injection-molding manner. Since the mold has a cavity corresponding to a predetermined shape, the formed transparent plastic material has a geometric appearance corresponding to the predetermined shape.

Abstract: Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented.

Abstract: Disclosed is a resin composition for encapsulating a semiconductor containing an epoxy resin (A), a curing agent (B), and an inorganic filler (C), wherein the epoxy resin (A) includes an epoxy resin (A1) having a predetermined structure, and the curing agent (B) includes a phenol resin (B1) having a predetermined structure, wherein the content of a c=1 component included in the total amount of the phenol resin (B1) is not less than 40% in terms of area percentage and the content of a C?4 component is not more than 20% in terms of area percentage, as measured by the area method of gel permeation chromatography. Also disclosed is a semiconductor device obtained by encapsulating a semiconductor element with a cured product of the resin composition for encapsulating a semiconductor.

Abstract: An integrated circuit package system includes a bottom pad with a bottom tie bar, attaching an integrated circuit die over the bottom pad, attaching a top pad with a top tie bar, over the integrated circuit die, and applying an encapsulant wherein the top tie bar integral to the top pad, is exposed on a side of the encapsulant.

Abstract: A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Abstract: A substrate on which a plurality of epoxy over molded integrated circuit dies are formed includes a beam formed on the substrate for providing stiffness to the substrate. The beam includes structure having a cross-sectional shape, for example, substantially in the shape of a trapezoid, “T” or “L”, and may be formed on the top or bottom surface of the substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.

Abstract: A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a conductive bump formed over the substrate and a semiconductor die with an active surface oriented to the substrate. An encapsulant is deposited over the semiconductor die and the conductive bump, and the encapsulant is planarized to expose a back surface of the semiconductor die opposite the active surface while leaving the encapsulant covering the conductive bump. A channel is formed into the encapsulant to expose the conductive bump. The channel extends vertically from a surface of the encapsulant down through the encapsulant and into a portion of the conductive bump. The channel extends through the encapsulant horizontally along a length of the semiconductor die. A shielding layer is formed over the encapsulant and the back surface of the semiconductor die.

Abstract: A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature coupled to the active circuitry that protrudes from the bottomside surface or the topside semiconductor surface. The topside semiconductor surface and/or bottomside surface and the protruding feature are coated with a dielectric polymer. A portion of the dielectric polymer is removed from the protruding feature using a solvent to expose a tip portion of the protruding feature for electrical connection thereto. With a solvent that does not corrode or oxidize the exposed protruding feature tips, the need for a conventional subsequent chemical exposure to remove corrosion or oxidation is avoided.

Abstract: A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.

Abstract: A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.

Abstract: The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the side surfaces is positioned at a boundary between the first area and the second area, a plurality of pads formed over the main surface of the semiconductor substrate and a plurality of external connecting terminals formed thereon, which are respectively electrically connected to the pads, a first resin portion which is formed over the main surface of the semiconductor substrate so as to cover the pads and has a main surface and side surfaces, and which is formed in such a manner that the external connecting terminals are exposed from the main surface and each of the side surfaces is positioned at the boundary, and a second resin portion which is positioned in the second area and formed so as to cover the side surfaces of the s

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.

Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.

Abstract: A method for producing multiple semiconductor devices. An electrically conductive layer is applied onto a semiconductor wafer. The semiconductor wafer is structured to produce multiple semiconductor chips. The electrically conductive layer is structured to produce multiple semiconductor devices.

Abstract: An object is to provide an insulating film for a semiconductor device which has characteristics of a low permittivity, a low leakage current, and a high mechanical strength, undergoes less change in these characteristics with the elapse of time, and has an excellent water resistance, as well as to provide a process and an apparatus for producing the insulating film for a semiconductor device, a semiconductor device, and a process for producing the semiconductor device.

Abstract: A semiconductor package structure and a package process are provided, wherein a lower surface of a die pad of a leadframe is exposed by an encapsulant so as to improve the heat dissipation efficiency of the semiconductor package structure. In addition, two chips are disposed at the same sides of the leadframe and the end portion of each of leads bonding to the upper chip is encapsulated by the encapsulant such that the scratch on the lead tips in wire bonding and die attach steps can be prevented and thus the wire bondability can be enhanced.

Abstract: Disclosed is a granular resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, satisfying the following requirements (a) to (c) on condition that ion viscosity is measured with a dielectric analyzer under a measurement temperature of 175° C. and a measurement frequency of 100 Hz: (a) the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity is 20 seconds or shorter; (b) the lowest ion viscosity value is not more than 6.5; and (c) the time interval between the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity and the time from the initiation of the measurement until the ion viscosity reaching 90% of an ion viscosity value measured at 300 seconds is 10 seconds or longer.

Abstract: The positive tone photosensitive composition of the invention comprises an alkali-soluble resin having a phenolic hydroxyl group, a compound producing an acid by light, a thermal crosslinking agent and an acrylic resin. It is possible to provide a positive tone photosensitive composition that can be developed with an aqueous alkali solution, has sufficiently high sensitivity and resolution, and can form a resist pattern with excellent adhesiveness and thermal shock resistance.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.

Abstract: According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the corners of a semiconductor chip, is provided. The semiconductor chip mounting body includes a circuit board having a circuit pattern formed on a mounting surface thereof, a semiconductor chip mounted on the circuit pattern of the circuit board, and a bonding member arranged at least between the circuit board and the semiconductor chip, and on the sides of the semiconductor chip to fix the semiconductor chip on the circuit board. The bonding member contains thermosetting resin and magnetic powder dispersed in the thermosetting resin. The magnetic powder is locally disposed in portions of the bonding member which is located the corners of the semiconductor chip.

Abstract: An organic protective film 23? is formed on the periphery of a chip region 12 on a substrate 11 so as to continuously surround the internal part of the chip region 12. A passivation film 22 and an organic protective film 23 form a closed-loop opening on a cap layer 47.

Abstract: A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.

Abstract: In various embodiments, the present invention relates to production of encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and applying a stimulus to said first solution system to induce simultaneous aggregation of the nanoparticles and the encapsulating medium.

Abstract: A polymer layer is generated on a wafer. The wafer is then separated into semiconductor chips. At least two semiconductor chips are placed on a carrier with the polymer layer facing the carrier. The at least two semiconductor chips are covered with an encapsulating material to form an encapsulant. The carrier is removed from the encapsulant, and the encapsulant and the polymer layer are thinned.

Abstract: A method for producing a microfluid component includes: Producing a single polymer layer made of at least one plastic or a plastic composite and having a microfluid structure, fitting the polymer layer with at least one semiconductor element, and/or with at least one electronic component, and/or with an optical or optoelectronic component, sealing the microfluid structure.

Abstract: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.

Abstract: According to an embodiment, a separation layer and a wiring layer having an organic insulating film formed of a resin material and a metal wiring are sequentially formed on a support substrate. Regions of the organic insulating film corresponding to dicing regions are removed. Plural semiconductor chips are mounted on the wiring layer. A sealing resin layer is formed on the separation layer. The sealing resin layer is formed to cover edge surfaces of the device forming regions. The support substrate is separated from a resin sealing body having the wiring layer, the plural semiconductor chips and the sealing resin layer. The resin sealing body is cut according to the dicing regions to cingulate a structure configuring a semiconductor device.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.

Abstract: A curable organopolysiloxane composition and an optical semiconductor element sealant, each comprising (A) a diorganopolysiloxane that has at least 2 alkenyl groups wherein at least 70 mole % of all the siloxane units are methylphenylsiloxane units and the total content of 1,3,5-trimethyl-1,3,5-triphenylcyclotrisiloxane and 1,3,5,7-tetramethyl-1,3,5,7-tetraphenylcyclotetrasiloxane is no more than 5 weight %, (B) an organopolysiloxane that has at least 2 silicon-bonded hydrogen atoms wherein at least 15 mole % of the silicon-bonded organic groups are phenyl groups, and (C) a hydrosilylation reaction catalyst. An optical semiconductor device in which an optical semiconductor element within a housing is sealed with the cured product from the aforementioned composition.

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Abstract: In a double-sided electrode package, a sealing resin layer is formed so as to fill peripheries of surface-side terminals formed on a package substrate. Since the side surfaces of the surface-side terminals have plural protruded rims, adhesion with the sealing resin layer is improved by an anchor effect. At a sealing step, since supplied liquid resin is naturally flowed to form the sealing resin layer, a “mold step” and a “grinding step” may be omitted, and thus the sealing step may be simplified more greatly than a case where the resin sealing is carried out by a transfer molding method.

Abstract: A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer.

Abstract: A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.

Abstract: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant.