Comprising Antifuses, I.e., Connections Having Their State Changed From Nonconductive To Conductive (epo) Patents (Class 257/E23.147)
E Subclasses
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Publication number: 20090206381Abstract: An anti-fuse includes a gate dielectric layer formed over a substrate, a gate electrode including a body portion and a plurality of protruding portions extending from the body portion, wherein the body portion and the protruding portions are formed to contact on the gate dielectric layer, and a junction region formed in a portion of the substrate exposed by sidewalls of the protruding portions.Type: ApplicationFiled: February 12, 2009Publication date: August 20, 2009Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon
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Publication number: 20090206447Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
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Publication number: 20090189248Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.Type: ApplicationFiled: January 30, 2009Publication date: July 30, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Eiji KITAMURA, Shinichi HORIBA, Nobuyuki NAKAMURA
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Publication number: 20090189182Abstract: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Inventors: Uwe Hodel, Wolfgang Soldner
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Patent number: 7557424Abstract: A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements.Type: GrantFiled: January 3, 2007Date of Patent: July 7, 2009Assignee: International Business Machines CorporationInventors: Keith Kwong Hon Wong, Chih-Chao Yang, Haining S Yang
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Patent number: 7544968Abstract: An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.Type: GrantFiled: August 24, 2005Date of Patent: June 9, 2009Assignee: Xilinx, Inc.Inventors: Shahin Toutounchi, James Karp, Jongheon Jeong, Michael G. Ahrens, Michael J. Hart
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Publication number: 20090140299Abstract: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and by using a diode having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.Type: ApplicationFiled: February 6, 2009Publication date: June 4, 2009Applicant: SANDISK 3D LLCInventors: Xiaoyu Yang, Roy E. Scheuerlein, Feng Li, Albert T. Meeks
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Patent number: 7538369Abstract: A resistance-change-type fuse circuit has a plurality of polysilicon fuses which are made of polysilicon and causes irreversible change in resistance by flowing a current; a plurality of programming transistors which are provided corresponding to the plurality of fuses, each programming transistor switching whether to flow the current through the corresponding fuse to cause change in resistance with respect to the polysilicon fuses, a dummy fuse group including a plurality of dummy fuses having the same electrical properties as that of the polysilicon fuses, each dummy fuse having 1/n (n is an integer equal to or more than 1) times a resistance of the polysilicon fuses, a dummy transistor circuit which has at least one of dummy transistor having 1/n times a conductance of the programming transistors, a gate and a drain of the dummy transistor being connected to each other, and a current mirror circuit including the programming transistor and the dummy transistor, the current mirror circuit causing each polysiType: GrantFiled: April 27, 2007Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Natsuki Kushiyama
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Patent number: 7531886Abstract: A one-time programmable field effect transistor (FET) e-fuse has a silicided gate connected to the drain while the source is grounded. A voltage stimulus applied to the drain forces current to flow through the channel coupling the drain to the source. The magnitude of the current exceeding the threshold current density initiates electromigration of the source/drain silicide into the channel region, such that the source/drain of the FET is shorted to the substrate after programming. Under these constraints, the fuse device conducts current even when the transistor is in the off-state. The MOSFET e-fuse preferably uses a minimum channel length NFET/PFET and scales down its dimensions to conform to those allowed by the technology.Type: GrantFiled: July 6, 2006Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventors: Satya N. Chakravarti, Thekkemadathil V. Rajeevakumar, Timothy J. Sullivan
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Publication number: 20090102014Abstract: An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.Type: ApplicationFiled: December 23, 2005Publication date: April 23, 2009Applicants: STMicroelectronics Crolles 2 SAS, France and Koninklijke Philips Electronics N.V.Inventors: Bertrand Borot, Roberto Maurizio Gonella, Sebastien Fabre
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Publication number: 20090096060Abstract: Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.Type: ApplicationFiled: June 30, 2008Publication date: April 16, 2009Inventors: Deok-kee Kim, Yoon-dong Park, Seung-hoon Lee, I-hun Song, Won-joo Kim, Young-gu Jin, Hyuk-soon Choi, Suk-pil Kim
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Publication number: 20090057820Abstract: An abrupt MIT (metal-insulator transition) device with parallel conducting layers is provided. The abrupt MIT device includes a first electrode disposed on a certain region of a substrate, a second electrode disposed so as to be spaced a predetermined distance apart from the first electrode, and at least one conducting layer electrically connecting the first electrode with the second electrode and having a width that allows the entire region of the conducting layer to be transformed into a metal layer due to an MIT. Due to this configuration, deterioration of the conducting layer, which is typically caused by current flowing through the conducting layer, is less likely to occur.Type: ApplicationFiled: January 31, 2007Publication date: March 5, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Hyun-Tak Kim, Byung-Gyu Chae, Kwang-Yong Kang, Bong-Jun Kim, Yong-Wook Lee, Sun-Jin Yun
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Publication number: 20090052221Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.Type: ApplicationFiled: August 22, 2008Publication date: February 26, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Sumio OGAWA
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Publication number: 20090026577Abstract: To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown.Type: ApplicationFiled: July 24, 2008Publication date: January 29, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Sumio Ogawa
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Publication number: 20090008742Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.Type: ApplicationFiled: August 31, 2007Publication date: January 8, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasunori OKAYAMA
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Publication number: 20090008741Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.Type: ApplicationFiled: August 31, 2007Publication date: January 8, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasunori OKAYAMA
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Publication number: 20080296697Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of said interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in said standard interposer to an integrated circuit die encapsulated in said electronic package. Methods of forming said programmable semiconductor interposer and said electronic package are also illustrated.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
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Publication number: 20080296728Abstract: A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Daniel C. Edelstein, Jack A. Mandelman, Louis L. Hsu
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Publication number: 20080283964Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.Type: ApplicationFiled: June 23, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Nicholas C. Fuller, Louis C. Hsu
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Publication number: 20080277756Abstract: An electronic device is disclosed having a dielectric layer (12) formed at a semiconductor substrate (10). A polysilicon fuse structure (14) having a first length is formed overlying the dielectric layer (12). First and second portions (141, 142) of the polysilicon fuse structure are silicided, wherein a third portion (143) of the polysilicon fuse structure (114) that abuts the first portion (141) and the second portion (142) of the polysilicon fuse remains unsilicided.Type: ApplicationFiled: May 9, 2007Publication date: November 13, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Won Gi Min, Jiang-Kai Zuo
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Publication number: 20080224260Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.Type: ApplicationFiled: March 12, 2008Publication date: September 18, 2008Applicant: EASIC CORPORATIONInventors: Herman Schmit, Ronnie Vasishta, Adam Levinthal, Jonathan Park
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Publication number: 20080197450Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1±0.4, and the ratio of x to y in SixNy is in a range of about 0.75±0.225.Type: ApplicationFiled: April 15, 2008Publication date: August 21, 2008Applicants: ACTEL CORPORATION, TEXAS TECH UNIVERSITY SYSTEMInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Publication number: 20080185723Abstract: An antifuse includes a first conductor pattern, a sidewall insulating film formed on a side of the first conductor pattern, and a second conductor pattern formed so that the sidewall insulating film is interposed between the first and second conductor patterns and so as to face the side of the first conductor pattern. The antifuse utilizes the sidewall insulating film as a capacitor insulating film of a capacitor.Type: ApplicationFiled: February 5, 2008Publication date: August 7, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Yoshikazu Moriwaki
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Patent number: 7405463Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.Type: GrantFiled: June 26, 2006Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, John D. Porter
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Patent number: 7402463Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.Type: GrantFiled: August 19, 2005Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Nicholas C. Fuller, Louis C. Hsu
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Publication number: 20080122026Abstract: The invention is directed to an improved eFUSE that prevent rupturing of the fuse link, reduces current through the fuse link, and optimizes electromigration through the fuse link through the use of a feedback circuit.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Deok-Kee Kim, Haining Yang
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Patent number: 7358589Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.Type: GrantFiled: August 23, 2005Date of Patent: April 15, 2008Assignee: Actel CorporationInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Patent number: 7351613Abstract: A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).Type: GrantFiled: November 4, 2004Date of Patent: April 1, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Bomy Chen, Ya-Fen Lin, Zhitang Song, Songlin Feng
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Patent number: 7329911Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.Type: GrantFiled: February 9, 2005Date of Patent: February 12, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Yasunori Okayama
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Patent number: 7323761Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.Type: GrantFiled: November 12, 2004Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Byeongju Park, Subramanian S. Iyer, Chandrasekheran Kothandaraman
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Patent number: 7319053Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.Type: GrantFiled: February 14, 2006Date of Patent: January 15, 2008Assignee: SanDisk 3D LLCInventors: Vivek Subramanian, James M. Cleeves
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Publication number: 20080009105Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.Type: ApplicationFiled: September 13, 2007Publication date: January 10, 2008Inventor: S. Herner
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Patent number: 7301216Abstract: A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.Type: GrantFiled: October 5, 2004Date of Patent: November 27, 2007Assignee: United Microelectronics Corp.Inventors: Chiu-Te Lee, Te-Yuan Wu
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Patent number: 7256471Abstract: An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The high electric field created at the end corners (120, 122) of the gate electrode (104) results in a breakdown and rupture of the insulating layer (110) at points directly beneath the end corners (120, 122). This localization of the insulating layer (110) at the corners (120,122) provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements (102) when integrated into an array (300, 320, 400, 550) provide for increased packing density. The array is fabricated to include multiple active areas (304) for individual antifuse element (302) programming or a common active area (324,405,426,506) for multi-element programming.Type: GrantFiled: March 31, 2005Date of Patent: August 14, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Won Gi Min, Robert W. Baird, Jiang-Kai Zuo, Gordon P. Lee
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Patent number: 7253496Abstract: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. In another embodiment, current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. In yet another embodiment, dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.Type: GrantFiled: September 29, 2005Date of Patent: August 7, 2007Assignee: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, John Kizziar
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Patent number: 7226816Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.Type: GrantFiled: February 11, 2005Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, Jack A. Mandelman, William R. Tonti
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Publication number: 20070120221Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).Type: ApplicationFiled: January 26, 2007Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Fifield, Wagdi Abadeer, William Tonti
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Publication number: 20070102786Abstract: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such that the first insulating film is in contact with a surface of the fuse; and a second insulating film formed on the first insulating film; wherein the second insulating film has an opening therein formed above a fuse region of the uppermost wiring layer such that only the first insulating film exists above the fuse region, the fuse region including the fuse and being irradiated with a laser beam when the fuse is blown.Type: ApplicationFiled: October 23, 2006Publication date: May 10, 2007Applicant: Renesas Technology Corp.Inventors: Yasuhiro Ido, Takeshi Iwamoto
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Patent number: 7206215Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film. Embodiments include a method of operating an antifuse, comprising applying a voltage across electrodes of a capacitor having a tantalum oxynitride film and forming a hole in the tantalum oxynitride film.Type: GrantFiled: August 29, 2002Date of Patent: April 17, 2007Assignee: Micron Technology, Inc.Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
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Patent number: 7176065Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.Type: GrantFiled: May 6, 2005Date of Patent: February 13, 2007Assignee: Micron Technology, Inc.Inventors: Mirmajid Seyyedy, Mark E. Tuttle, Glen E. Hush
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Publication number: 20060289864Abstract: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.Type: ApplicationFiled: July 7, 2006Publication date: December 28, 2006Inventors: John Fifield, Russell Houghton, William Tonti
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Patent number: 7148503Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.Type: GrantFiled: October 3, 2001Date of Patent: December 12, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuya Fujimura, Toshiyuki Yokoyama, Kentaro Shiomi, Akira Motohara
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Patent number: 7071534Abstract: An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.Type: GrantFiled: September 1, 2004Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, Shubneesh Batra
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Patent number: 6919613Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.Type: GrantFiled: April 8, 2004Date of Patent: July 19, 2005Assignee: Micron Technology, Inc.Inventors: Mirmajid Seyyedy, Mark E. Tuttle, Glen E. Hush