Comprising Antifuses, I.e., Connections Having Their State Changed From Nonconductive To Conductive (epo) Patents (Class 257/E23.147)
E Subclasses
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Patent number: 8395232Abstract: A semiconductor device includes an antifuse element. The semiconductor device includes a first well of a first conductivity type disposed in a semiconductor substrate; a first insulating film on the first well; a first conductive film of the first conductivity type on the first insulating film; and an impurity-introduced region of the first conductivity type. The impurity-introduced region of the first conductivity type in the first well is higher in impurity concentration than the first well. The impurity-introduced region includes a first portion that faces toward the first conductive film through the first insulating film.Type: GrantFiled: July 14, 2010Date of Patent: March 12, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Horiba, Nobuyuki Nakamura, Eiji Kitamura
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Patent number: 8384131Abstract: The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.Type: GrantFiled: August 6, 2008Date of Patent: February 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Andrew Tae Kim, Hong-Jae Shin
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Publication number: 20130037859Abstract: A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Inventors: Huicai Zhong, Qingqing Liang, Chao Zhao, Huilong Zhu
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Patent number: 8368172Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.Type: GrantFiled: July 22, 2011Date of Patent: February 5, 2013Assignee: Freescale Semiconductor, Inc.Inventors: George R. Leal, Kevin J. Hess, Trent S. Uehling
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Patent number: 8367483Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8368069Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8368070Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8361887Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.Type: GrantFiled: January 31, 2012Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Alberto Cestero, Byeongju Park, John M. Safran
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Patent number: 8361886Abstract: A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material.Type: GrantFiled: December 2, 2010Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventors: Yoshitaka Kubota, Takuji Onuma
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Publication number: 20130020674Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Inventors: GEORGE R. LEAL, Kevin J. Hess, Trent S. Uehling
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Patent number: 8357994Abstract: An antifuse is disclosed which has an electrically-insulating region sandwiched between two electrodes. The electrically-insulating region has a single layer of a non-hydrogenated silicon-rich (i.e. non-stoichiometric) silicon nitride SiNX with a nitrogen content X which is generally in the range of 0<X?1.2, and preferably 0.5?X?1.2. The breakdown voltage VBD for the antifuse can be defined to be as small as a few volts for CMOS applications by controlling the composition and thickness of the SiNX layer. The SiNX layer thickness can also be made sufficiently large so that Poole-Frenkel emission will be the primary electrical conduction mechanism in the antifuse. Different types of electrodes are disclosed including electrodes formed of titanium silicide, aluminum and silicon. Arrays of antifuses can also be formed.Type: GrantFiled: March 1, 2006Date of Patent: January 22, 2013Assignee: Sandia CorporationInventors: Scott D. Habermehl, Roger T. Apodaca
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Publication number: 20130009278Abstract: A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die.Type: ApplicationFiled: June 14, 2012Publication date: January 10, 2013Inventor: Hoon LEE
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Patent number: 8350264Abstract: An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region.Type: GrantFiled: July 14, 2010Date of Patent: January 8, 2013Assignee: International Businesss Machines CorporationInventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Patent number: 8330189Abstract: A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.Type: GrantFiled: June 21, 2010Date of Patent: December 11, 2012Assignee: Kilopass Technology, Inc.Inventors: Harry S. Luan, Yue-Song He, Ting-Wah Wong
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Patent number: 8330249Abstract: An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit.Type: GrantFiled: April 6, 2010Date of Patent: December 11, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hajime Tokunaga
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Patent number: 8330250Abstract: A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.Type: GrantFiled: September 11, 2011Date of Patent: December 11, 2012Assignee: SanDisk 3D LLCInventor: Scott Brad Herner
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Patent number: 8324708Abstract: Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.Type: GrantFiled: September 22, 2010Date of Patent: December 4, 2012Assignee: Seiko Instruments Inc.Inventors: Yukimasa Minami, Masaru Akino
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Patent number: 8299569Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.Type: GrantFiled: July 8, 2011Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventor: Takehiro Ueda
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Publication number: 20120261795Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.Type: ApplicationFiled: June 28, 2012Publication date: October 18, 2012Applicant: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
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METHOD FOR CONTROLLING THE ELECTRICAL CONDUCTION BETWEEN TWO METALLIC PORTIONS AND ASSOCIATED DEVICE
Publication number: 20120248568Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.Type: ApplicationFiled: March 30, 2012Publication date: October 4, 2012Applicant: STMicroelectronics (Crolles 2) SASInventor: Serge Blonkowski -
Publication number: 20120248546Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
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Patent number: 8278732Abstract: An antifuse element for an integrated circuit is provided, including a conductive region formed in a semiconductor substrate, extending along a first direction; a dielectric layer formed on a portion of the conductive region; a first conductive plug formed on the dielectric layer; a second conductive plug formed on another portion of the conductive region; and a first conductive member formed over the first and second conductive plugs, extending along a second direction perpendicular to the first direction; and a second conductive member formed over the second conductive plug extending along the second direction, wherein the first conductive member intersects with the conductive region, having a first overlapping area therebetween, and the dielectric layer and the conductive region have a second overlapping area therebetween, and a ratio between the first overlapping area and the second overlapping area is about 1.5:1 to 3:1.Type: GrantFiled: April 28, 2011Date of Patent: October 2, 2012Assignee: Nanya Technology CorporationInventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20120228724Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
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Patent number: 8258586Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: GrantFiled: March 11, 2011Date of Patent: September 4, 2012Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
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Patent number: 8242578Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.Type: GrantFiled: March 25, 2011Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
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Publication number: 20120199943Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Sumio OGAWA
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Patent number: 8232146Abstract: A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same.Type: GrantFiled: October 27, 2010Date of Patent: July 31, 2012Assignee: Seiko Intruments Inc.Inventor: Yuichiro Kitajima
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Patent number: 8227890Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: GrantFiled: December 18, 2009Date of Patent: July 24, 2012Assignee: United Microelectronics CorporationInventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Patent number: 8217490Abstract: Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second terminals; and control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube block can switch between a plurality of electronic states in response to a plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube block provides an electrical pathway of different resistance between the first and second terminals.Type: GrantFiled: August 8, 2007Date of Patent: July 10, 2012Assignee: Nantero Inc.Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold, Jonathan W. Ward, Darren K. Brock
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Patent number: 8211755Abstract: A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein a pillar comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer. The method further comprises depositing a dielectric between the plurality of semiconductor pillars, and plasma etching a deep via recess through the dielectric and through the underlying layer after the steps of forming a plurality of semiconductor pillars and depositing a dielectric. An embodiment of the invention comprises a memory array device.Type: GrantFiled: May 5, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Lan Kuo, Kern-Huat Ang
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Patent number: 8193074Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.Type: GrantFiled: November 21, 2008Date of Patent: June 5, 2012Assignee: SanDisk 3D LLCInventor: Yoichiro Tanaka
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Publication number: 20120126366Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120126367Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120126365Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section.Type: ApplicationFiled: January 19, 2012Publication date: May 24, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Shinsuke Tani, Toshiyuki Nakaiso
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Patent number: 8183665Abstract: A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles. A second conductive terminal is in physical and electrical contact with the article. Select circuitry is arranged in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.Type: GrantFiled: November 19, 2008Date of Patent: May 22, 2012Assignee: Nantero Inc.Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
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Patent number: 8179709Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.Type: GrantFiled: August 22, 2008Date of Patent: May 15, 2012Assignee: Elpida Memory, Inc.Inventor: Sumio Ogawa
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Patent number: 8178945Abstract: Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p? substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p? substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.Type: GrantFiled: February 2, 2010Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Ping-Chuan Wang, Robert C. Wong, Haining S. Yang
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Publication number: 20120112313Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers on the upper and lower surfaces of the insulation layer; and an extraction electrode formed so as to make contact with a section of the electrode layers that form electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section including short circuit sections that are short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by engulfing the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. Furthermore, the extraction electrode has at least two or more sections in contact with the electrode layer.Type: ApplicationFiled: January 20, 2012Publication date: May 10, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Shinsuke Tani, Toshiyuki Nakaiso
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Publication number: 20120104545Abstract: An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Inventors: Yutaka Takeshima, Toshiyuki Nakaiso, Shinsuke Tani
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Publication number: 20120104544Abstract: A semiconductor device adapted such that written information cannot be analyzed even by using a method of analyzing the presence or absence of electric charge, accumulated on a gate electrode, in which a substrate is a first conduction type, for example, p-type semiconductor substrate (for example, silicon substrate), an antifuse has a gate electrode and a second conduction type diffusion layer, the second conduction type diffusion layer is formed in the substrate and has, for example, an n-conduction type, a first contact is connected to the gate electrode, second contacts are formed in a layer identical with the first contact and connected to a region of the substrate in which the second conduction type diffusion layer is not formed, and the second contact is adjacent to the first contact.Type: ApplicationFiled: October 17, 2011Publication date: May 3, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yoshitaka KUBOTA
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Publication number: 20120091557Abstract: An anti-fuse of a semiconductor device and a method for manufacturing the same are disclosed. In order to achieve stable operation of the anti-fuse, a gate rupture prevention film is formed between a gate pattern and a source/drain junction region and a gate oxide film is formed at both ends of a lower edge of the gate pattern. Therefore, when applying a voltage, the overlapped gate oxide film is ruptured so that a current level is stabilized and the anti-fuse is stably operated.Type: ApplicationFiled: October 14, 2011Publication date: April 19, 2012Applicant: Hynix Semiconductor Inc.Inventor: Jin Hwan LEE
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Patent number: 8159042Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.Type: GrantFiled: June 23, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Nicholas C. Fuller, Louis C. Hsu
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Publication number: 20120061796Abstract: A mechanically programmable anti-fuse is configured in a thick, top metallic layer of a semiconductor. The metallic layer is selected of a material that possesses malleable properties. The metal anti-fuse programming pad is surrounded, either wholly or in part, by a pad segment. An intervening space between the anti-fuse pad and the pad segment is selected from a predetermined value such that capillary pressure, exerted when a ball-bond is placed atop the anti-fuse pad and the pad segment, causes the pads to deform and shorts to the anti-fuse pad to the pad segment. The shorting, created during the wire bonding process, programs the anti-fuse.Type: ApplicationFiled: September 14, 2010Publication date: March 15, 2012Inventor: James Jen-Ho Wang
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Publication number: 20120061797Abstract: According to one embodiment, a semiconductor device including a substrate, and an anti-fuse element including a first insulator formed on the substrate, a conductive film formed on the first insulator, the conductive film including a silicide film, a contact formed on the substrate, the contact being disposed adjacent to the conductive film with a second insulator interposed between the contact and the conductive film, the contact being short-circuited to the silicide film.Type: ApplicationFiled: March 7, 2011Publication date: March 15, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masahiko Kanda
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Patent number: 8134220Abstract: Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.Type: GrantFiled: June 16, 2008Date of Patent: March 13, 2012Assignee: Nantero Inc.Inventors: H. Montgomery Manning, Thomas Rueckes, Jonathan W. Ward, Brent M. Segal
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Patent number: 8125048Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: October 7, 2009Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8125013Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.Type: GrantFiled: August 14, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: David S. Collins, Kai D. Feng, Zhong-Xiang Ile, Peter J. Lindgren, Robert M. Rassel
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Patent number: 8124971Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.Type: GrantFiled: March 30, 2007Date of Patent: February 28, 2012Assignee: SanDisk 3D LLCInventor: Yoichiro Tanaka
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Patent number: 8115275Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.Type: GrantFiled: September 8, 2009Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Alberto Cestero, Byeongju Park, John M. Safran
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Patent number: 8110893Abstract: A fuse element utilizing a reaction between two layers by feeding current is manufactured. A fuse element including a first layer formed of an oxide or a nitride and a second layer that becomes high resistant by nitridation or oxidation, in which the first layer and the second layer are in contact with each other, is manufactured. For example, the fuse element is manufactured by using indium tin oxide for the first layer and aluminum for the second layer. By generating joule heat by applying voltage to the first layer and the second layer, oxygen in the indium tin oxide enters the aluminum, which changes the aluminum into aluminum oxide that presents an insulating property. The fuse element can be manufactured by a similar process as that of forming a TFT.Type: GrantFiled: July 15, 2010Date of Patent: February 7, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kengo Akimoto