Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.

Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.

Abstract: An electrical device includes a substrate; first and second active areas; first and second word lines disposed in a first plane; first and second bit lines in a second plane and in electrical communication with first and second active areas; and a reference line disposed in a third plane. A nanotube element disposed in a fourth plane is in electrical communication with first and second active areas and the reference line via electrical connections at a first surface of the nanotube element. The nanotube element includes first and second regions having resistance states that are independently adjustable in response to electrical stimuli, wherein the first and second regions nonvolatilely retain the resistance states. Arrays of such electrical devices can be formed as nonvolatile memory devices. Methods for fabricating such devices are also disclosed.

Abstract: The present invention provides a thin semiconductor device in which its security such as prevention of counterfeit or information leakage is to be enhanced. One feature of the present invention is a thin semiconductor device in which a plurality of thin film integrated circuits are mounted and in which at least one integrated circuit is different from the other integrated circuits in any one of a specification, layout, frequency for transmission or reception, a memory, a communication means, a communication rule and the like. According to the present invention, a thin semiconductor device tag having the plurality of thin film integrated circuits communicates with a reader/writer and at least one of the thin film integrated circuits receives a signal to write information in a memory, and the information written in the memory determines which of the thin film integrated circuits communicates.

Abstract: A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and an aromatic ring-containing compound, the aromatic ring-containing compound including at least one of a moiety represented by the following Chemical Formula 1 and a moiety represented by the following Chemical Formula 2:

Abstract: Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips.

Abstract: A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and a compound, the compound including a structural unit represented by the following Chemical Formula 1:

Abstract: A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material.

Abstract: In an example, a method of fabricating one or more vertical interconnects is provided. The method includes patterning and stacking a plurality of wafers to form a wafer stack. A plurality of apertures can be formed in the wafer stack within one or more saw streets of the wafer stack, and conductive material can be deposited on sidewalls of the plurality of apertures.

Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.

Abstract: High-speed memory systems that consume a reduced amount of board space, have a low height or profile, or both. This reduction in board space and height may result in shorter signal paths from a board to a memory device, thereby improving the high-speed performance of the high-speed memory system. One example may provide a space-efficient memory system that consumes a reduced amount of board space. Space efficiency may gained by arraying memory devices on an interposer that mates with a socket attached to a board. Another example may provide a memory system that has a reduced height or profile. This reduced height may be achieved by employing a socket that accepts an interposer in a lateral or rotational direction.

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract: There has been very little (if any) attention to address contamination diffusion within an integrated circuit (IC) because there are very few applications where a protective overcoat will be penetrated as part of the manufacturing process. Here, a sealing ring is provided that address this problem. Preferably, the sealing ring uses the combination of electrically conductive barrier rings and the tortuous migration path to allow an electronic device (i.e., thermopile), where a protective overcoat is penetrated during manufacture, to communicate with external devices while being isolated to prevent contamination.

Abstract: A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap.

Abstract: Stray light in an oblique direction penetrates a channel part of a thin-film transistor, which sometimes causes light leakage current. This phenomenon becomes more pronounced in the case of using an optical system with high intensity, leading to deterioration in an image quality. To prevent the light that possibly penetrates an equivalent optical waveguide from reaching the channel part, on the condition that a first insulating layer is set to have a layer-thickness t (nm) and a refraction index n, a relation is to be expressed by the following expression. t<(0.61×?)/(n×sin ?) A value of ? is set to a lower limit 400 (nm) of a visible light wavelength and a value Lc (nm) is set to a distance between an end of a light-shielding layer and an end of a channel region. With those values, an expression of nt2/244 (nm)<Lc (nm) is set up.

Abstract: A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.

Abstract: An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

Abstract: A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type ca

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.

Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Abstract: A size variable semiconductor chip includes a semiconductor chip area formed with a circuit layer and at least one cutting area extending parallel to at least one side of the semiconductor chip area. A plurality of scribe line parts and a plurality of active parts alternately formed with each other in the cutting area.

Abstract: An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed.

Abstract: A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed on the main semiconductor region, preferably between gate and drain, is a Schottky electrode electrically coupled to the source. The Schottky electrode provides a Schottky diode in combination with the main semiconductor region. A current flow is assured from Schottky electrode to drain without interruption by a depletion region expanding from the gate.

Abstract: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.

Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.

Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: On a carrier (1) an adhesion layer (4), an ASIC chip (2) and a sensor chip (3) are arranged one above another. An interchip connection (5) is provided for electrically connecting the chips among one another, and an ASIC connection (6) is provided for externally electrically connecting the circuit integrated in the ASIC chip.

Abstract: Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

Abstract: Example embodiments of the invention may provide for a multi-package system. The multi-package system may include a first package having a plurality of first organic dielectric layers, where the first package includes at least one first conductive layer positioned between two of the plurality of first organic dielectric layers, and where the at least one first conductive layer is circuitized to form at least one first passive device. The multi-package system may also include a second package having a plurality of second organic dielectric layers, where the second package includes at least one second conductive layer positioned between two of the plurality of second organic dielectric layers, and where the at least one second conductive layer is circuitized to form at least one second passive device. An electrical connector may be provided between a bottom surface of the first package and a top surface of the second package to electrically connect the first package and the second package.

Abstract: In a fabricating method of a pixel structure, a scan line and a gate electrode are formed in each pixel area of a substrate. A gate insulation layer is formed to cover the scan line and gate electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. A data line, source and drain are formed in each pixel area. A first passivation layer covers the data line, source and drain. A common line is formed on the first passivation layer and overlaps with at least a portion of the data line. A common electrode is formed on and electrically connected with the common line. A second passivation layer covers the common electrode and common line. A contact window is formed in the second passivation layer above the drain to expose the drain. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.

Abstract: A semiconductor device including a capacitor having a lower electrode in which the lower electrode includes a first cylindrical lower electrode connected to a contact electrically connected to a semiconductor substrate; and a second cylindrical lower electrode in contact with an inner wall of at least an upper end of the first cylindrical lower electrode and extending upwards from a top of the first cylindrical lower electrode.

Abstract: A thin film transistor array panel includes: a substrate, a gate line disposed on the substrate, a data line intersecting the gate line, a drain electrode separated from the data line a first insulating layer covering the data line, a color filter disposed on the first insulating layer, a second insulating layer disposed on the color filter and having a contact hole exposing the drain electrode and the color filter and a pixel electrode disposed on the second insulating layer and connected to the drain electrode through the contact hole. The contact hole partially exposes the color filter near a portion where the drain electrode and the pixel electrode are connected to each other, and the pixel electrode covers the color filter exposed through the contact hole.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode of the switching element; a power supply line of the driver circuit; and a capacitor connected between the power supply line and the reference voltage line.

Abstract: A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which respectively pass through the first region and the second region, wherein a variable spacing lies between the first conductive line and the second conductive line and the first conductive line and the second conductive line selectively have a first region line width and a second region line width so that the first region line width and the second region line width are substantially different.

Abstract: The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated circuit comprises at least an integrated circuit transistor pair having a gate of a first transistor connected to a gate of a second transistor. The gate of the second transistor is designed such that it has a predetermined overlap with respect to a source and a drain of the second transistor. A detection circuit is connected to the at least an integrated circuit transistor pair for detecting if in operation functionality of the second transistor of each of the at least an integrated circuit transistor pair is one of a transistor and a short circuit. The integrated circuit is then manufactured in dependence upon the desogn. After manufacturing, the detection circuit is used to determine the functionality of the second transistor of each of the at least an integrated circuit transistor pair.

Abstract: A thin film transistor (TFT) substrate includes a substrate, data lines, scan lines and pixel electrodes. The data lines and the scan lines intersect each other on the substrate for defining pixel areas. The pixel electrodes are disposed in corresponding pixel areas. Each of the pixel electrodes defines at least two slits by which the pixel electrode is divided into at least two first areas and at least two second areas. The first areas and the second areas are insulated with respect to each other. The first areas are disposed diagonally and the second areas are disposed diagonally.

Abstract: The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed.

Abstract: An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.

Abstract: A method for manufacturing passive devices and semiconductor packages using a thin metal piece is provided. According to the method, an adhesive layer is formed on a dummy substrate; a thin metal piece is bonded on the adhesive layer; a masking material is attached to the thin metal piece, a dielectric layer is formed; a masking material is attached to form metal pads; a metal pad is formed, and the formed device is attached to a lower substrate using the metal pads; the adhesive layer and the dummy substrate are removed, a masking material is attached on a surface exposed, a region where passive devices are to be formed is patterned, and the thin metal piece is etched at a predetermined depth; and solder bumps for surface mounting are formed.

Abstract: According to the preferred embodiment, an integrated capacitor having a key-shaped structure is provided. The integrated capacitor comprises a first pair of key-shaped metal patterns and a second pair of key-shaped metal patterns. The first pair of key-shaped metal patterns engages with the second pair of key-shaped metal patterns, and a dielectric layer is situated therebetween.

Abstract: A commercially mass-produced ultra-miniaturized solid state system for using an ultraminiaturized atomic or molecular integrated circuit with gigabit memory and picosecond speed to automatically perform self-optimizing tasks selected from the group consisting of searching, tracking, teletraining, telelearning, telemedical diagnosis or treatment, and implanting knowledge or skill