Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A thin film field effect transistor including, on a substrate, at least a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein an electric resistance layer is provided in electric connection between the active layer and at least one of the source electrode or the drain electrode.

Abstract: A structure including at least two neighboring components, capable of operating at high frequencies, formed in a thin silicon substrate extending on a silicon support and separated therefrom by an insulating layer, the components being laterally separated by insulating regions. The silicon support has, at least in the vicinity of its portion in contact with the insulating layer, a resistivity greater than or equal to 1,000 ohms.cm.

Abstract: A display device includes a substrate, a white light source on the substrate, a dichroic layer between a viewing surface of the display device and the white light source, the dichroic layer being configured to allow light of a predetermined wavelength band to be transmitted therethrough, and a ¼ wavelength layer between the dichroic layer and the white light source.

Abstract: A thin film circuit comprises a plurality of thin film transistors, each having a light shield portion (60) which is electrically isolated from the source (72), drain (70) and gate (76) electrodes. The light shield portion comprises a first, drain overlap portion in which the light shield portion overlaps the drain conductor (70), a second, source overlap portion in which the light shield portion overlaps the source conductor (72), and a third, gate overlap portion in which the light shield portion overlaps the gate conductor (76) only. In one embodiment, at least ? of the light shield portion area comprises the gate overlap portion. In another embodiment, one of the source and drain overlap portions has at least 1.5 times the area of the other of the source and drain overlap portions. The use of an electrically floating light shield simplifies the layer construction and design.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

Abstract: A display device in which gate drive circuits are formed at both sides of an effective screen, and a static charge shield conductive film is formed to cover the gate drive circuits. In the manufacturing step and after producing the display device, the constant voltage is applied to the static charge shield conductive film via the common pad, the earth connection line and the like.

Abstract: A display panel includes a first substrate, a thin-film transistor (TFT), an organic layer, a second substrate, a seal line, and a conductive pattern. The first substrate includes a pixel part and a driving part connected to the pixel part. The TFTs are formed in the pixel part and the driving part. The organic layer is formed on the first substrate having the TFTs formed thereon. The second substrate is opposite to the first substrate. The seal line is disposed between an edge portion of the first substrate having the organic layer formed thereon and an edge portion of the second substrate. The seal line combines the first substrate with the second substrate. The conductive pattern is disposed between the seal line and the organic layer.

Abstract: Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.

Abstract: Stray light in an oblique direction penetrates a channel part of a thin-film transistor, which sometimes causes light leakage current. This phenomenon becomes more pronounced in the case of using an optical system with high intensity, leading to deterioration in an image quality. To prevent the light that possibly penetrates an equivalent optical waveguide from reaching the channel part, on the condition that a first insulating layer is set to have a layer-thickness t (nm) and a refraction index n, a relation is to be expressed by the following expression. t<(0.61×?)/(n×sin ?) A value of ? is set to a lower limit 400 (nm) of a visible light wavelength and a value Lc (nm) is set to a distance between an end of a light-shielding layer and an end of a channel region. With those values, an expression of nt2/244 (nm)<Lc (nm) is set up.

Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: The invention discloses a decoupling capacitor circuit, comprising a plurality of coupled deep trench capacitors connected in series and a plurality of push-pull circuits. The decoupling capacitor circuit controls the voltage across each deep trench capacitor via the push-pull circuit so that it will not be influenced by the defect (leakage current) of the deep trench capacitor or the bias voltage of the parasitic devices.

Abstract: In order to protect a semiconductor component against overvoltages, the steps which are used for production of bipolar transistors and CMOS structures in the semiconductor component are used for integrated parallel production of a zener diode. This has a first and a second n-doped zone, which extend between the surface of a semiconductor substrate and an n-doped buried region. The first n-doped zone is oppositely doped with p-doping in an area adjacent to the surface, and represents a p-doped region. A first contact is provided to the p-doped region, and a contact is on the other hand provided to the second n-doped zone, with the two contents forming the two connections of the zener diode.

Abstract: Provided is a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor includes a pixel array unit having a matrix-type array of unit pixels, each unit pixel including a charge transfer element transferring charge collected in a photoelectric conversion element to a charge detection element. The charge transfer element also receives a boosted voltage signal higher than an external power voltage.

Abstract: In a light sensing element having simplified structure, an array substrate having the light sensing element and an LCD apparatus having the light sensing element, the light sensing element includes a first electrode, a control electrode and a second electrode. An alternating bias voltage is applied to the first electrode. An off voltage is applied to the control electrode. The second electrode outputs a light-induced leakage current based on an externally provided light and the bias voltage. Therefore, the array substrate includes one light sensing switching element corresponding to one pixel so that structure of the array substrate is simplified and opening ratio is increased.

Abstract: A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single common collector layer and separated base layers on the common collector layer. The capacitance of the variable-capacitance element is generated between respective base layers of the PN junctions with the common collector layer, and varies in correspondence with the voltage applied to the common collector layer.

Abstract: An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Abstract: A highly integrated radio front-end module. In one embodiment a semiconductor substrate is processed with various circuit components in the substrate, as well as interconnections for the various circuit components, embedding the circuit components into the substrate. One or more circuit components may be further connected with a separate integrated circuit, the separate integrated circuit bonded to the semiconductor substrate via contact points processed into the substrate.

Abstract: The present invention relates to a semiconductor device comprising at least one static random access memory (SRAM) cell with self-aligned contacts. Specifically, the at least one SRAM cell comprises at least a first gate conductor that is located over a channel region between a source region and a drain region. The first gate conductor is covered by a dielectric cap comprising a protective dielectric material, and the source and drain regions are covered by non-protective dielectric material(s) that can be selectively removed against the protective material. In this manner, a self-aligned source or drain contact can be formed through the non-protective dielectric material(s) to contact either the source or the drain region, while the dielectric cap protects the first gate conductor during formation of the source or drain contact opening and thereby prevents shorting between the first gate conductor and the source or drain contact to be formed.

Abstract: Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.

Abstract: A semiconductor device including inductors with improved reliability and a method of manufacturing the same are provided. The semiconductor device may include a substrate, an insulating film pattern formed on the substrate and having an opening, an amorphous metal nitride film formed inside the opening, a diffusion reducing or preventing film formed on the amorphous metal nitride film, and a conductive film including the diffusion reducing or preventing film filling the inside of the opening.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. A second set of trenches, perpendicular to the first set, is formed to separate columns of the array. Word lines are formed along rows of the array. The word lines are formed into the second set of trenches in order to shield adjacent floating gates. Metal shields are formed in the first set of trenches along the rows and between floating gates on the pillars.

Abstract: The electronic device (10) comprises a capacitor (12) and an inductor (11) and is present on a substrate (1) with an unplanarized surface (2). This is realized in winding (21) of the inductor (11) has a thickness of at least 1 micron and has a planarized upper surface (81). The upper electrode (32) of the capacitor is present in a second electrode layer (6) and has a lower surface (82) which is spaced from the substrate (1) by a larger distance than the upper surface (81) of the lower electrode (31). The second electrode layer (6) preferably includes a second winding (22) of the inductor (11). The electronic device (10) is suitable for use at high frequencies.

Abstract: One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.

Abstract: A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

Abstract: An electronic component arrangement includes a discrete electronic component having first and second terminals and a centre-exposed pad. A substrate has a first electrical conductor electrically connected to the first terminal, a second electrical conductor electrically connected to the second terminal, and a third electrical conductor. A thermally conductive element is in direct thermal communication with both the centre-exposed pad of the electronic component and the third electrical conductor of the substrate.

Abstract: A voltage-dividing resistor enables a multi-step voltage division. The voltage-dividing resistor includes a polysilicon layer formed on a semiconductor substrate; a metal layer formed on a partial area of the polysilicon layer; an insulating interlayer covering the polysilicon layer and the metal layer; a first electrode for applying a first reference voltage to one end of the polysilicon layer; a second electrode for applying a second reference voltage to the other end of the polysilicon layer; a plurality of third electrodes provided between the first and second electrodes to contact the metal layer; and a plurality of fourth electrodes provided between the first and second electrodes to contact the polysilicon layer.