Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

Abstract: A gate structure includes a gate insulation layer, a gate electrode and a capping layer pattern. The gate insulation layer is formed on an inner wall of a recess in a substrate. The gate electrode is formed on the gate insulation layer to partially fill the recess. The capping layer pattern is formed of silicon oxide on the gate electrode and the gate insulation layer to fill a remaining portion of the recess.

Abstract: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

Abstract: A semiconductor device as described herein includes a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region. A gate control region of the first conductivity type adjoins the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region. A source zone of the second conductivity type is arranged within the body region and a channel stop zone of the second conductivity type is arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region. The channel stop zone includes a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone.

Abstract: The present invention provides an anti-fuse of a semiconductor device and a method of manufacturing the same, which has a stable current level and a stable operation. According to the present invention, in order for the anti-fuse to be stably operated, a region in which a gate and an active region partially overlap with each other is formed, and the overlapped region is destroyed when voltage is supplied. Accordingly, a current level can be stabilized, and stable operation is possible.

Abstract: A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface.

Abstract: The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer.

Abstract: Monolithic electronic devices are providing including a high bandgap layer. A first type of nitride device is provided on a first portion of the high bandgap layer, the first nitride device including first and second implanted regions respectively defining source and drain regions of the first type of nitride device. A second type of nitride device, different from the first type of nitride device, is provided on a second portion of the high bandgap layer, the second type of nitride device including an implanted highly conductive region. At least a portion of the implanted highly conductive region of the second type of nitride device is coplanar with at least a portion of both the first and second implanted regions of the first type of nitride device.

Abstract: The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

Abstract: There is provided an electronic device having high reliability and high color reproducibility. A pixel structure is made such that a switching FET (201) and an electric current controlling FET (202) are formed on a single crystal semiconductor substrate (11), and an EL element (203) is electrically connected to the electric current controlling PET (202). The fluctuation in characteristics of the electric current controlling FET (202) is very low among pixels, and an image with high color reproducibility can be obtained. By taking hot carrier measures in the electric current controlling FET (202), the electronic device having high reliability can be obtained.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.

Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

Abstract: A power switch with active snubber. In accordance with a first embodiment, an electronic circuit includes a first power semiconductor device and a second power semiconductor device coupled to the first power semiconductor device. The second power semiconductor device is configured to oppose ringing of the first power semiconductor device.

Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.

Abstract: An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region. An SCRMOS transistor with a RESURF region around the drain region and SCR terminal. A process of forming an integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal.

Abstract: A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer.

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract: Semiconductor memory devices and methods of forming the same are provided, the semiconductor memory devices include a first and a second buried gate respectively disposed on both inner sidewalls of a groove formed in an active portion and a device isolation pattern. The first and second buried gates are controlled independently from each other.

Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.

Abstract: The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.

Abstract: A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.

Abstract: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.

Abstract: In a gated anti-fuse, an anode is separated from a cathode by an oxide layer and the anode or cathode voltage is controlled by the control gate of a transistor like structure connected to the anode or cathode.

Abstract: A thin film transistor array panel can include: a substrate; a gate line formed on the substrate; a gate pad formed at an end of the gate line; a gate identification member corresponding to the gate pad and formed in the same layer as the gate pad; a gate insulating layer covering the gate line and the gate identification member; a data line formed on the gate insulating layer; a passivation layer formed on the gate insulating layer and the data line; a gate contact assistant formed on the passivation layer; and a gate driving chip electrically connected to the gate contact assistant, wherein the gate contact assistant at least partially overlaps the gate identification member. The gate identification member is formed without producing a step in the gate contact assistant, reducing the risk of defects when wires or other objects are pressed onto the gate pad.

Abstract: The present invention relates to using a potentially trap-rich layer, such as a polycrystalline Silicon layer, over a passivation region of a semiconductor substrate or a Silicon-on-insulator (SOI) device layer to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate or SOI device layer at radio frequency (RF) frequencies. The potentially trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.

Abstract: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire channel layer, and specifically is formed in a region near the surface of the channel layer. Since the ZnCl is strong enough not to be decomposed when exposed to plasma etching gas, an increase in the carrier concentration can be prevented. The distribution of ZnCl in the channel layer, may result from the inclusion of chlorine (Cl) in the plasma gas during the patterning of the channel layer.

Abstract: An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.

Abstract: Monolithic electronic device including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. First and second pluralities of contacts respectively define first and second electronic devices on the common nitride epitaxial layer.

Abstract: Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current.

Abstract: There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer.

Abstract: A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing port

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract: A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level.

Abstract: A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Abstract: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.

Abstract: An n? type semiconductor region is provided with an n? diffusion region serving as a drain region, and at one side of the n? diffusion region a p diffusion region and an n+ diffusion region serving as a source region are provided. At an other side of the n? diffusion region a trench is provided and has an insulator introduced therein. Immediately under the n? diffusion region a p? buried layer is provided. In a region of the n? semiconductor region an n+ diffusion region to which a high potential is applied is provided and electrically connected to the n? diffusion region by an interconnect having a resistor. On a surface of a portion of the p diffusion region that is sandwiched between the n+ diffusion region and the n? diffusion region a gate electrode is provided, with a gate insulation film posed therebetween.

Abstract: A semiconductor device having high reliability and high load short circuit withstand capability while maintaining a low ON resistance is provided, by using a WBG semiconductor as a switching element of an inverter circuit. In the semiconductor device for application to a switching element of an inverter circuit, a band gap of a semiconductor material is wider than that of silicon, a circuit that limits a current when a main transistor is short circuited is provided, and the main transistor that mainly serves to pass a current, a sensing transistor that is connected in parallel to the main transistor and detects a microcurrent proportional to a current flowing in the main transistor, and a lateral MOSFET that controls a gate of the main transistor on the basis of an output of the sensing transistor are formed on the same semiconductor.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: A field-effect transistor includes at least a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, which are formed on a substrate. The channel layer is made of an amorphous oxide material that contains at least In and B, and the amorphous oxide material has an element ratio B/(In+B) of 0.05 or higher and 0.29 or lower.

Abstract: A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Abstract: In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

Abstract: An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.

Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.