Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).

Abstract: Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode of MIS•FET constituting the main circuit. In the main circuit region, an insulating film made of a silicon nitride film is formed to cover the gate electrode, whereby miniaturization of elements in the main circuit region is not impaired. The memory cell array has no such insulating film. This means that the upper surface of the floating gate electrode is not contiguous to the insulating film but is covered directly with an interlayer insulating film. According to such a constitution, leakage of electrons from the floating gate electrode of the memory cell array can be suppressed or prevented and the flash memory thus obtained has improved data retention characteristics.

Abstract: Monolithic electronic devices including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first type of nitride device, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. A first plurality of electrical contacts are provided on the first at least one implanted n-type region.

Abstract: A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.

Abstract: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect, and a second impurity diffusion layers. The first fuse interconnect, the second fuse interconnect, and the first impurity diffusion layer of each of the plurality of fuse element portions are arranged approximately parallel to one another at a predetermined pitch distance.

Abstract: An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.

Abstract: There is provided an electronic device having high reliability and high color reproducibility. A pixel structure is made such that a switching FET (201) and an electric current controlling FET (202) are formed on a single crystal semiconductor substrate (11), and an EL element (203) is electrically connected to the electric current controlling FET (202). The fluctuation in characteristics of the electric current controlling FET (202) is very low among pixels, and an image with high color reproducibility can be obtained. By taking hot carrier measures in the electric current controlling FET (202), the electronic device having high reliability can be obtained.

Abstract: An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: In the present invention, an electron injection composition for a light-emitting element, comprising a pyridine derivative represented by general formula 1 and at least one of an alkali metal, an alkali earth metal, and a transition metal, is used to form an electron injection layer in a portion of a layer including luminescent material in a light-emitting element, and it is also an object of the present invention to provide, by using the composition, a light-emitting element that has more superior characteristics and a longer lifetime as compared to conventional ones. (where each of R1 to R8 represents hydrogen, halogen, a cyano group, an alkyl group having 1 to 10 carbon atoms, a haloalkyl group having 1 to 10 carbon atoms, an alkoxyl group having 1 to 10 carbon atoms, a substituted or unsubstituted aryl group, or a substituted or unsbstituted heterocyclic group.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.