Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Abstract: A semiconductor device includes a plurality of first gate electrodes that are arranged above a semiconductor substrate in a first direction, and a plurality of second gate electrodes that are arranged above the semiconductor substrate in a second direction. The semiconductor device further includes a first gate lead-out electrode to which the first gate electrodes are connected, a second gate lead-out electrode to which the second gate electrodes are connected, and a third gate lead-out electrode to which the first gate lead-out electrode and the second gate lead-out electrode are connected. In the semiconductor device according to the present invention, a punched pattern is formed in the third gate lead-out electrode.

Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Abstract: A method of forming a semiconductor device includes forming a device isolation region in a silicon substrate to define an nMOS region and a pMOS region. A p-well is formed in the nMOS region and an n-well in the pMOS region. Gate structures are formed over the p-well and n-well, each gate structure including a stacked structure comprising a gate insulating layer and a gate electrode. A resist mask covers the nMOS region and exposes the pMOS region. Trenches are formed in the substrate on opposite sides of the gate structures of the pMOS region. SiGe layers are grown in the trenches of the pMOS region. The resist mask is removed from the nMOS region. Carbon is implanted to an implantation depth simultaneously on both the nMOS region and the pMOS region to form SiC on the nMOS region and SiGe on the pMOS region.

Abstract: A nitride semiconductor device according to the present invention includes: a nitride semiconductor laminated structure comprising a first layer made of a Group III nitride semiconductor, a second layer laminated on the first layer and made of an Al-containing Group III nitride semiconductor with a composition that differs from that of the first layer, the nitride semiconductor laminated structure comprising a stripe-like trench exposing a lamination boundary between the first layer and the second layer; a gate electrode formed to oppose the lamination boundary; and a source electrode and a drain electrode, having the gate electrode interposed therebetween, each connected electrically to the second layer.

Abstract: A display apparatus includes a thin film transistor array panel including a display region and a non-display region, a gate line extending along a first direction, a data line extending along a second direction, substantially perpendicular to the first direction, the data line being insulated from and crossing the gate line, a storage electrode line which receives a common voltage signal, and a first gate driver disposed on the thin film transistor array panel and which supplies at least one of a gate on signal and a gate off signal to the gate line. The storage electrode line includes a first portion extending along the first direction and a second portion extending along the second direction in the non-display region. A width, measured along the second direction, of the first portion is less than a width, measured along the first direction, of the second portion.

Abstract: A semiconductor device includes: a semiconductor region of first conductivity type provided in a semiconductor layer of first conductivity type; a first semiconductor region of second conductivity type; a second semiconductor region of second conductivity type; a third semiconductor region of second conductivity type having a lower impurity concentration than the second semiconductor region of second conductivity type; a first insulating layer provided in the third semiconductor region of second conductivity type; a control electrode provided on the semiconductor region of first conductivity type via a second insulating layer; a first auxiliary electrode provided on the first insulating layer; a first main electrode electrically connected to the first semiconductor region of second conductivity type; and a second main electrode electrically connected to the second semiconductor region of second conductivity type.

Abstract: A SGPMOS transistor includes a base, a P-type diffusion layer, a gate electrode, and a LOCOS oxide film. The base includes at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well. The P-type diffusion layer includes a P-type source and a P-type drain. At least the P-type drain includes a double diffusion structure including first and second P-type drain diffusion layers. The LOCOS oxide film is provided on the first P-type drain diffusion layer and covered by an end of the gate electrode. The first and the second P-type drain diffusion layers satisfy a relation of Y<Xj, in which Y represents a distance of the first P-type drain diffusion layer between the second P-type drain diffusion layer and the channel, and Xj represents a difference between depths of the second P-type drain diffusion layer and the first P-type drain diffusion layer.

Abstract: A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate having a semiconductor surface, the semiconductor surface including at least a first surface region that provides a first dopant type. A patterned masking layer is formed on the first surface region, wherein at least one aperture in the masking layer is defined. The first surface region is etched to form at least one trench region corresponding to a position of the aperture. A dopant of a first dopant type is implanted to raise a concentration of the first dopant type in a first dopant type drift region located below the trench region. After the implanting, the trench region is filled with a dielectric fill material. A body region is then formed having a second dopant type in a portion of the first surface region. A gate dielectric is then formed over a surface of the body region and the first surface region.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.

Abstract: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.

Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

Abstract: In a conventional semiconductor device, protection of a to-be-protected element from a surge voltage is difficult because the to-be-protected element is turned on before a protection element due to variations in manufacturing conditions. In a semiconductor device of the present invention, a protection element and a MOS transistor have part of their structures formed under common conditions. N type diffusion layers of the protection element and the MOS transistor are formed in the same process, while the N type diffusion layer of the protection element has a larger diffusion width than the N type diffusion layer of the MOS transistor. With this structure, when a surge voltage is applied to an output terminal, the protection element is turned on before the MOS transistor, and thereby the MOS transistor is protected from an avalanche current.

Abstract: In relation to the conventional semiconductor device provided with a plurality of FETs, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region (certain region). The four have each of gate electrodes, respectively. Each of the gate electrodes are arranged along a circle in this sequence in plan view. The four FETs have the substantially same geometry.

Abstract: An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second protrudent portions, second P+ diffusion regions disposed between the PMOS transistor and the second protrudent portions, second N+ diffusion regions disposed between the NMOS transistor and the first protrudent portions, third P+ diffusion regions disposed between the NMOS transistor, the boundary, and two adjacent second P+ diffusion regions, and third N+ diffusion regions disposed between the PMOS transistor, the boundary, and two adjacent second N+ diffusion regions, wherein the first and second protrudent portions are interlacedly arranged at the boundary.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Abstract: A sub-substrate, a blue-violet semiconductor laser device, an insulating layer, and a red semiconductor laser device are stacked in order on a support member through a plurality of fusion layers. The insulating layer is stacked on an n-side pad electrode of the blue-violet semiconductor laser device, and a conductive layer is formed on the insulating layer. The red semiconductor laser device is stacked on the conductive layer through a fusion layer. The conductive layer is electrically connected to a p-side pad electrode of the red semiconductor laser device. The n-side pad electrode of the blue-violet semiconductor laser device and the n-side pad electrode of the red semiconductor laser device are electrically connected to each other.

Abstract: Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method.

Abstract: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire channel layer, and specifically is formed in a region near THE surface of the channel layer. Since the ZnCl is strong enough not to be decomposed when exposed to plasma etching gas, an increase in the carrier concentration can be prevented. The distribution of ZnCl in the channel layer, may result from the inclusion of chlorine (Cl) in the plasma gas during the patterning of the channel layer.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.

Abstract: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.

Abstract: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.

Abstract: A semiconductor device is disclosed that includes a nonvolatile memory cell having a memory transistor and a selection transistor, and a peripheral circuit transistor. The memory transistor includes a memory gate oxide film that is arranged on a semiconductor substrate, and a floating gate made of polysilicon that is arranged on the memory gate oxide film. The selection transistor is serially connected to the memory transistor and includes a selection gate oxide film that is arranged on the semiconductor substrate, and a selection gate made of polysilicon that is arranged on the selection gate oxide film. The peripheral circuit transistor includes a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film. The memory gate oxide film is arranged to be thinner than the peripheral circuit gate oxide film.

Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.

Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

Abstract: Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M1).

Abstract: An electrostatic discharge (ESD) protection circuit electrically connected to a first conductive line and a second conductive line is provided. The ESD protection circuit has a first ESD protection circuit unit, wherein the first ESD circuit unit includes a first coupled capacitor and a first active device. The first coupled capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conductive line. The first active device includes a first gate, a first source and a first drain, wherein the first gate is electrically connected to the second electrode. In addition, the first source and the first electrode are electrically connected to the first conductive line, and the first drain is electrically connected to the second conductive line. Therefore, the conduction efficiency of the ESD protection circuit is improved.

Abstract: A semiconductor device is disclosed. One embodiment provides a top surface. A first lateral semiconductor region is arranged adjacent to the top surface and includes a transistor structure. The transistor structure includes a drain zone of a first conductivity type. A second lateral semiconductor region is arranged below the first semiconductor region and includes a junction field-effect transistor structure. The junction field-effect transistor structure includes a source zone of the first conductivity type which is electrically connected to the drain zone of the transistor structure.

Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

Abstract: In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.

Abstract: A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

Abstract: A semiconductor integrated circuit device includes a first dopant region in a semiconductor substrate, an isolation region on the semiconductor substrate, the isolation region surrounding the first dopant region, a gate wire surrounding at least a portion of the isolation region, and a plurality of second dopant regions arranged along at least a portion of the gate wire, the plurality of second dopant regions being spaced apart from each other, and the portion of the gate wire being between the first dopant region and a respective second dopant region.

Abstract: A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.

Abstract: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

Abstract: A SGPMOS transistor includes a base, a P-type diffusion layer, a gate electrode, and a LOCOS oxide film. The base includes at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well. The P-type diffusion layer includes a P-type source and a P-type drain. At least the P-type drain includes a double diffusion structure including first and second P-type drain diffusion layers. The LOCOS oxide film is provided on the first P-type drain diffusion layer and covered by an end of the gate electrode. The first and the second P-type drain diffusion layers satisfy a relation of Y<Xj, in which Y represents a distance of the first P-type drain diffusion layer between the second P-type drain diffusion layer and the channel, and Xj represents a difference between depths of the second P-type drain diffusion layer and the first P-type drain diffusion layer.

Abstract: A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract: A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.

Abstract: Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting an element across the source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: A semiconductor device including: a bulk semiconductor substrate; an access transistor; a thruster formed on the bulk semiconductor substrate connecting to the access transistor; an element separating region to separate the region for the access transistor and the region for the thruster from each other; and a wiring layer connecting one of the diffused layers of the access transistor and the cathode of the thruster together through a connecting hole, the impurity region at the anode side of the thruster being composed of a p-type impurity region, an n-type impurity region, p-type impurity region, and an n-type impurity region, which are formed sequentially in the depth wise direction, with the lowermost n-type impurity region receiving the same voltage as that applied to the anode at the time of data holding.

Abstract: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.

Abstract: An n? type semiconductor region is provided with an n? diffusion region serving as a drain region, and at one side of the n? diffusion region a p diffusion region and an n+ diffusion region serving as a source region are provided. At an other side of the n? diffusion region a trench is provided and has an insulator introduced therein. Immediately under the n? diffusion region a p? buried layer is provided. In a region of the n? semiconductor region an n+ diffusion region to which a high potential is applied is provided and electrically connected to the n? diffusion region by an interconnect having a resistor. On a surface of a portion of the p diffusion region that is sandwiched between the n+ diffusion region and the n? diffusion region a gate electrode is provided, with a gate insulation film posed therebetween.