In Combination With Diode, Resistor, Or Capacitor (epo) Patents (Class 257/E27.016)
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Publication number: 20100289080Abstract: In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.Type: ApplicationFiled: April 14, 2010Publication date: November 18, 2010Inventors: Andy WEI, Andrew WAITE
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Publication number: 20100283931Abstract: In a TFT array substrate (20), connecting points (P10) of a first metal layer (M1) and a second metal layer (M2) are provided in a peripheral region (A20). A driving circuit (B60b), which is at least a part of a driving circuit (60), is provided between the connecting points (P10) and an edge (24) of the TFT array substrate (20).Type: ApplicationFiled: December 2, 2008Publication date: November 11, 2010Inventors: Satoshi Horiuchi, Takaharu Yamada, Isao Ogasawara
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Patent number: 7829928Abstract: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep wells are separated but partially linked with each other.Type: GrantFiled: June 26, 2006Date of Patent: November 9, 2010Assignee: System General Corp.Inventors: Chiu-Chih Chiang, Chih-Feng Huang
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Publication number: 20100276740Abstract: A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.Type: ApplicationFiled: July 12, 2010Publication date: November 4, 2010Inventors: Thanas Budri, Jiankang Bu
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Patent number: 7825435Abstract: A silicon-made low-forward-voltage Schottky barrier diode is serially combined with a high-antivoltage-strength high-electron-mobility transistor made from a nitride semiconductor that is wider in bandgap than silicon. The Schottky barrier diode has its anode connected to the gate, and its cathode to the source, of the HEMT. This HEMT is normally on. The reverse voltage withstanding capability of the complete device depends upon that between the drain and gate of the HEMT.Type: GrantFiled: January 16, 2008Date of Patent: November 2, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Osamu Machida, Akio Iwabuchi
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Patent number: 7821099Abstract: A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.Type: GrantFiled: May 12, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Publication number: 20100264456Abstract: A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Anton Mauder, Hans-Joachim Schulze, Helmut Strack
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Publication number: 20100265622Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.Type: ApplicationFiled: April 15, 2009Publication date: October 21, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. CAMPI, JR., Shunhua T. CHANG, Kiran V. CHATTY, Robert J. GAUTHIER, JR., Junjun LI, Mujahid MUHAMMAD
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Patent number: 7812424Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.Type: GrantFiled: December 21, 2007Date of Patent: October 12, 2010Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Helmut Horst Tews
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Publication number: 20100254050Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.Type: ApplicationFiled: April 7, 2009Publication date: October 7, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsin Tang, Jian-Hsing Lee
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Publication number: 20100252894Abstract: A non-volatile memory devices includes: a substrate including a circuit device and a metal line electrically connected with the circuit device; a diode connected with the metal line in a vertical direction with respect to a surface of the substrate, and including a metal layer disposed on a lower part of the diode facing the surface of the substrate; and a resistor electrically connected with the diode in series.Type: ApplicationFiled: March 11, 2010Publication date: October 7, 2010Applicant: Samsung Electronics Co., Ltd.Inventor: Byung Sup Shim
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Publication number: 20100243744Abstract: An object is to provide a semiconductor device which operates stably even when the communication distance between a reader/writer and a non-contact data carrier is largely changed. A protection circuit is provided in the non-contact data carrier, and an operating state and a non-operating state of the protection circuit are switched depending on the communication distance between the reader/writer and the non-contact data carrier. The operating point at which the operating state and the non-operating state of the protection circuit are switched is different between the case where input voltage of the protection circuit is low in an initial state and then gradually raised and the case where input voltage of the protection circuit is high in an initial state and then gradually lowered.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Masashi FUJITA
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Publication number: 20100244137Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: ApplicationFiled: June 10, 2010Publication date: September 30, 2010Inventors: Keiichi YOSHIZUMI, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
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Publication number: 20100244110Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.Type: ApplicationFiled: March 22, 2010Publication date: September 30, 2010Inventors: Hui-Jung KIM, Young-Chul Oh, Jae-Man Yoon, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim
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Publication number: 20100244756Abstract: A high voltage integrated circuit contains a freewheeling diode embedded in a transistor. It further includes a control block controlling a high voltage transistor and a power block—including the high voltage transistor—isolated from the control block by a device isolation region. The high voltage transistor includes a semiconductor substrate of a first conductivity type, a epitaxial layer of a second conductivity type on the semiconductor substrate, a buried layer of the second conductivity type between the semiconductor substrate and the epitaxial layer, a collector region of the second conductivity type on the buried layer, a base region of the first conductivity type on the epitaxial layer, and an emitter region of the second conductivity type formed in the base region. The power block further includes a deep impurity region of the first conductivity type near the collector region to form a PN junction.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Inventors: Taeg-hyun Kang, Sung-son Yun
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Publication number: 20100244092Abstract: A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.Type: ApplicationFiled: February 18, 2010Publication date: September 30, 2010Inventors: Katsumi ISHIKAWA, Kazutoshi Ogawa
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Patent number: 7804112Abstract: The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET.Type: GrantFiled: August 28, 2008Date of Patent: September 28, 2010Assignee: Rohm Co., Ltd.Inventor: Toshio Nakajima
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Publication number: 20100237395Abstract: A semiconductor device, such as a transistor or capacitor, is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate electrode film over the gate dielectric. The gate dielectric includes a mixed rare earth nitride or oxynitride film containing at least two different rare earth metal elements.Type: ApplicationFiled: May 17, 2010Publication date: September 23, 2010Applicant: TOKYO ELECTRON LIMITEDInventor: Robert D. Clark
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Publication number: 20100237435Abstract: A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.Type: ApplicationFiled: March 2, 2010Publication date: September 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Ricardo A. Donaton, William K. Henson, Yue Liang
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Publication number: 20100237421Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.Type: ApplicationFiled: February 9, 2010Publication date: September 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Gregory G. Freeman, Kevin McStay, Shreesh Narasimha
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Publication number: 20100237356Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.Type: ApplicationFiled: March 20, 2009Publication date: September 23, 2010Inventors: Sarah Kay Haney, Sei-Hyung Ryu
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Publication number: 20100237434Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention.Type: ApplicationFiled: June 22, 2006Publication date: September 23, 2010Applicant: NXP B.V.Inventors: Wibo D. Van Noort, Jan Sonsky, Philippe Meunier-Beillard, Erwin Hijzen
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Publication number: 20100237414Abstract: A trench MOSFET device with embedded Schottky rectifier, gate-drain and gate-source diodes on single chip is formed with shallow trench structure to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: FORCE MOS TECHNOLOGY CO., LTD.Inventor: Fu-Yuan Hsieh
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Publication number: 20100230733Abstract: According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate.Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Werner Juengling
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Publication number: 20100230717Abstract: A semiconductor device includes: a first semiconductor layer of non-doped AlXGa1-XN (0?X<1); a second semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) on the first semiconductor layer; a first electrode on the second semiconductor layer; a second electrode on the second semiconductor layer that is separated from the first electrode and electrically connected to the second semiconductor layer; a first insulating film covering the first and second electrodes; a first field plate electrode electrically connected to the first electrode and covered by a second insulating film; and a second field plate electrode on the second insulating film, wherein a length of at least one of the first and second field plate electrodes in a first direction from the first electrode toward the second electrode changes periodically in a second direction intersecting the first direction.Type: ApplicationFiled: February 24, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Wataru SAITO
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Patent number: 7795608Abstract: When to-be-detected light is made incident from a support substrate 2 side of a photocathode E1, a light absorbing layer 3 absorbs this to-be-detected light and produces photoelectrons. However, depending on the thickness and the like of the light absorbing layer 3, the to-be-detected light can be transmitted through the light absorbing layer 3 without being sufficiently absorbed by the light absorbing layer 3. The to-be-detected light transmitted through the light absorbing layer 3 reaches an electron emitting layer 4. A part of the to-be-detected light that has reached the electron emitting layer 4 proceeds toward a through-hole 5a of a contact layer 5. Since the length d1 of a diagonal line of the through-hole 5a is shorter than the wavelength of the to-be-detected light, the to-be-detected light can be suppressed from passing through the through-hole 5a and being emitted to the exterior.Type: GrantFiled: July 23, 2008Date of Patent: September 14, 2010Assignee: Hamamatsu Photonics K.K.Inventors: Toru Hirohata, Minoru Niigaki
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Publication number: 20100224924Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.Type: ApplicationFiled: March 4, 2010Publication date: September 9, 2010Applicant: Innovative Silicon ISi SAInventors: Wayne Ellis, John Kim
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Publication number: 20100224962Abstract: A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.Type: ApplicationFiled: February 3, 2010Publication date: September 9, 2010Inventor: Jongwon Kim
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Publication number: 20100224931Abstract: A trench DMOS transistor employing trench contacts has overvoltage protection for prevention of shortage between gate and source, comprising a plurality of first-type function trenched gates, at least one second-type function trenched gate and at least two third-type function trenched gates extending through body regions and into an epitaxial layer. The first-type function trenched gates are located in active area surrounded by a source region encompassed in the body region in the epitaxial layer for current conduction. The second-type function trenched gates are disposed underneath a gate metal with a gate trenched contacts filled with metal plug for gate metal connection. The third type function trenched gates are disposed directly and symmetrically underneath ESD trenched contact areas of anode and cathode in an ESD protection diode, serving as a buffer layer for prevention of gate-body shortage.Type: ApplicationFiled: May 21, 2010Publication date: September 9, 2010Applicant: FORCE MOS TECHNOLOGY CO. LTD.Inventor: Fu-Yuan Hsieh
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Patent number: 7790555Abstract: A semiconductor device manufacturing method includes a field oxide insulation film forming step, an electrode forming step, and a resistor forming step. The field oxide insulation film forming step comprises forming a field oxide insulation film on a surface of the semiconductor substrate so that a portion which corresponds to a side surface portion for each of active regions formed on the surface of the semiconductor substrate, which opposes a rotation center of the surface of the semiconductor substrate in spin-coating of a photoresist in the electrode forming step, and which is located at a front side of a centrifugal force acting direction along the surface of the semiconductor substrate has a curved surface that is convex in a forward direction of the centrifugal force along the surface of the semiconductor substrate as seen in plan view of the semiconductor substrate.Type: GrantFiled: May 21, 2007Date of Patent: September 7, 2010Assignee: Seiko Instruments Inc.Inventors: Akiko Tsukamoto, Hisashi Hasegawa, Jun Osanai
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Patent number: 7786522Abstract: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.Type: GrantFiled: March 17, 2009Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventors: H. Montgomery Manning, David H. Wells
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MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification
Patent number: 7786531Abstract: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.Type: GrantFiled: July 14, 2005Date of Patent: August 31, 2010Assignee: Alpha & Omega semiconductor Ltd.Inventors: Sik K. Lui, Anup Bhalla -
Publication number: 20100213521Abstract: A semiconductor device includes a back bias dielectric including a negative fixed charge, a gate electrode overlapping the back bias dielectric, a semiconductor layer disposed between the gate electrode and the back bias dielectric, and a gate dielectric disposed between the semiconductor layer and the gate electrode, wherein the negative fixed charge accumulates holes at a surface of the semiconductor layer facing the back bias dielectric.Type: ApplicationFiled: February 25, 2010Publication date: August 26, 2010Inventors: Sanghun Jeon, Jong-Hyuk Kang, Heungkyu Park, Jongwook Lee
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Publication number: 20100208400Abstract: The pad interface circuit includes a first stack MOS transistor having a first terminal connected to a pad and a bulk connected to a first supply voltage; a second stack MOS transistor having a first terminal connected to a second terminal of the first stack MOS transistor and a second terminal, a gate terminal, and a bulk that are connected to the first supply voltage; and a voltage level sensing circuit generating a feedback voltage by using a pad voltage applied from the pad. In addition, the feedback voltage is applied to a gate terminal of the first stack MOS transistor.Type: ApplicationFiled: January 21, 2010Publication date: August 19, 2010Inventors: Chan-hee Jeon, Han-gu Kim, Min-sun Hong, Tae-hoon Ha, Doo-hyung Kim, Jung-soon Lee
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Publication number: 20100193851Abstract: Provided is a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.Type: ApplicationFiled: April 12, 2010Publication date: August 5, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Kouichi Nagai
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Publication number: 20100193868Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Martin B. Mollat, Tony Thanh Phan
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Publication number: 20100193798Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Jun KOYAMA
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Publication number: 20100193869Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity-type, a buried diffusion layer of a second conductivity-type formed in the semiconductor substrate, a first well of the second conductivity-type having a bottom portion in contact with a top portion of the buried diffusion layer, the first well having an annular shape in a planar view, and a second well of the first conductivity-type formed to be surrounded by the first well. The semiconductor device further includes a diffusion region formed between a first portion of the second well and a second portion of the second well, the diffusion region having an impurity concentration lower than that of the second well, so that a depletion layer formed in the diffusion region can be provided, a transistor formed on the second well to function as an ESD (electro-static discharge) protection element, and an external terminal connected to a drain of the transistor.Type: ApplicationFiled: February 1, 2010Publication date: August 5, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Tadayuki Habasaki
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Publication number: 20100187586Abstract: A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.Type: ApplicationFiled: March 18, 2010Publication date: July 29, 2010Applicant: GLOBALFOUNDRIES INC.Inventors: Mario M. PELLELA, Donggang D. WU, James F. BULLER
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Publication number: 20100187598Abstract: There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.Type: ApplicationFiled: December 18, 2009Publication date: July 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi ENDO, Masaru IZUMISAWA, Takuma HARA, Syotaro ONO, Yoshiro BABA
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Publication number: 20100187640Abstract: A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.Type: ApplicationFiled: January 25, 2010Publication date: July 29, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventor: Takuji MIYATA
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Publication number: 20100187605Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: ApplicationFiled: January 27, 2009Publication date: July 29, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey
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Patent number: 7763923Abstract: A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of capacitor dielectric layers.Type: GrantFiled: December 29, 2005Date of Patent: July 27, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Der-Chyang Yeh, Chie-Iuan Lin, Chuan-Ying Lee, Yi-Ting Chao, Ming-Hsien Chen
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Patent number: 7763941Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.Type: GrantFiled: August 30, 2007Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Han-gu Kim, Ki-tae Lee, Jae-hyok Ko, Woo-sub Kim, Sung-pil Jang
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Publication number: 20100181627Abstract: A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.Type: ApplicationFiled: January 16, 2009Publication date: July 22, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Carolin Tolksdorf
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Publication number: 20100181547Abstract: A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers.Type: ApplicationFiled: December 29, 2009Publication date: July 22, 2010Applicant: Sony CorporationInventor: Hideaki Kuroda
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Publication number: 20100181607Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.Type: ApplicationFiled: March 29, 2010Publication date: July 22, 2010Inventors: Brian S. Doyle, Robert S. Chau, Vivek De, Suman Datta, Dinesh Somasekhar
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Patent number: 7759759Abstract: An integrated circuit includes a high voltage NPN bipolar transistor and a low voltage device. The NPN bipolar transistor includes a lightly doped p-well as the base region of the transistor while the low voltage devices are built using standard, more heavily doped p-wells. By using a process including a lightly doped p-well and a standard p-well, high and low voltage devices can be integrated onto the same integrated circuit. In one embodiment, the lightly doped p-well and the standard p-well are formed by performing ion implantation using a first dose to form the lightly doped p-well, masking the lightly doped p-well, and performing ion implantation using a second dose to form the standard p-well. The second dose is the difference of the dopant concentrations of the lightly doped p-well and the standard p-well. Other high voltage devices can also be built by incorporating the lightly doped p-well structure.Type: GrantFiled: July 25, 2005Date of Patent: July 20, 2010Assignee: Micrel IncorporatedInventor: Hideaki Tsuchiko
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Publication number: 20100176458Abstract: A gate insulating film is formed on a main surface of a substrate in which an element isolation region is formed. A metal film is formed on the gate insulating film. A silicon film is formed on the metal film. A gate electrode of a MIS transistor composed of a stacked structure of the silicon film and metal film is formed on an element region and a high-resistance element composed of a stacked structure of the silicon film and metal film is formed on the element isolation region by patterning the silicon film and metal film. An acid-resistant insulating film is formed on the side of the gate electrode. The metal film of the high-resistance element is oxidized. A diffused layer of the MIS transistor is formed in the substrate.Type: ApplicationFiled: January 12, 2010Publication date: July 15, 2010Inventor: Kazuaki NAKAJIMA
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Publication number: 20100176430Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit.Type: ApplicationFiled: March 10, 2010Publication date: July 15, 2010Applicant: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima