Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.

Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

Abstract: A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first word lines for respective first memory cells of the first memory block; a second memory block including second word lines for respective second memory cells of the second memory block; first diffusion regions coupled to the first word lines; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second word lines; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.

Abstract: The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack.

Abstract: A light source module including a ceramic substrate, copper traces, light emitting units, and heat conductive columns is provided. The first heat conductive column and the second heat conductive column correspond to the first light emitting unit and the second light emitting unit respectively. The negative electrode of the first light emitting unit is connected to the first copper trace, the positive electrode of the second light emitting unit is connected to the second copper trace, and the positive electrode of the first light emitting unit and the negative electrode of the second light emitting unit are connected to the third copper trace. An end of the first heat conductive column is connected to the positive electrode of the first light emitting unit, and an end of the second heat conductive column is connected to the negative electrode of the second light emitting unit.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.

Abstract: A technology for securing favorable appearance of a SiC member, the SiC member includes: a first SiC layer having a first upper surface having a concavo-convex shape and a first lower surface; and a second SiC layer having a second upper surface and a second lower surface, the second lower surface being in contact with the first upper surface and having a concavo-convex shape corresponding to that of the first upper surface. The second SiC layer has a recess concaved from the second upper surface toward the second lower surface side and a flat bottom surface, and the bottom surface of the recess is placed upward of the second lower surface.

Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Abstract: A semiconductor device includes a semiconductor substrate including a fin of semiconductor material having a fin width and a fin length. The fin length is greater than the fin width and extends between a first fin end and a second fin end. A gate electrode extends over the fin at a first fin location between the first fin end and the second fin end. A dummy gate electrode extends over the first fin end and is floating.

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

Abstract: According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) including a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a first source/drain region of the first switching device and a first source/drain region of the second switching device at a node. The controller is configured to alternatingly change the first and second switching devices between a first state and a second state, respectively. The first switching device is in a third state before or after the second switching device transitions between the first and second states. A subthreshold voltage is applied to a first gate of the first switching device during the third state, such that the third state is between a cutoff mode and a triode mode of the first switching device.

Abstract: Various embodiments disclosed in the disclosure relate to a flexible connection member and an electronic device comprising same, the flexible connection member having an RF line for signal transmission formed therein, wherein an impedance of the RF line is prevented from being changed even when a flexible printed circuit board is bent.

Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.

Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.

Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

Abstract: A semiconductor structure includes an array of two-port (TP) SRAM cells, each of which includes a write port and a read port. The write port includes two write pass gate (W_PG) transistors, two write pull-down (W_PD) transistors, and two write pull-up (W_PU) transistors. The array of TP SRAM cells includes first and second TP SRAM cells whose write ports abuts each other. Two W_PG transistors of the first and second TP SRAM cells share a common gate electrode. Source/drain electrodes of two W_PD transistors of the first and second TP SRAM cells share a common contact. The first TP SRAM cell includes a Vss conductor connected to the common contact. The second TP SRAM cell includes a write word line (W_WL) landing pad connected to the common gate electrode. The Vss conductor and the W_WL landing pad are located at a first metal layer.

Abstract: The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same.

Abstract: The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Abstract: A semiconductor device including first to fourth points defined using In ion intensity, Si concentration, and C concentration obtained from SIMS data. The active layer of the device is a first region between the first point and the second point. In addition, the C concentration in a third region between the third point and the fourth point is higher than the C concentration in a second region adjacent to the fourth region along a second direction. Also, the Si concentration in the second region is higher than the Si concentration in the third region.

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

Abstract: A system comprises a gate driver that is configured to couple to a transistor disposed in a transistor module via a first pin. The gate driver comprises a duty cycle measurement circuit having a first input terminal and a first output terminal, the first input terminal coupled to a second pin via an isolator. The duty cycle measurement circuit comprises a flip-flop, a counter, a shift register, and a comparator. The system comprises an analog to digital converter circuit having a second input terminal, a second output terminal, and a reference terminal, the second input terminal coupled to a third pin configured to couple to a temperature-sensitive device disposed in the transistor module, the second output terminal coupled to a fourth pin via the isolator, and the reference terminal coupled to the first output terminal.

Abstract: The present disclosure relates to a structure which includes a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply which is at a greater voltage than the low voltage power supply, and the high voltage power supply is output from the second current mirror leg circuit.

Abstract: An encoder according to an embodiment of this disclosure includes a voltage generation circuit connected to a power supply through a diode and having a variable resistor, the voltage generation circuit outputting a voltage corresponding to a current flowing through the diode and a resistance value of the variable resistor, as a threshold value; a comparator for performing a comparison between an analog signal inputted from a detector for detecting rotation of a motor and the threshold value inputted from the voltage generation circuit, and outputting a comparison result as a comparator output; a resistance value variation circuit for varying the resistance value of the variable resistor; and a threshold value determination circuit for determining the threshold value based on a relationship between the resistance value and the comparator output.

Abstract: An encoder according to an embodiment of this disclosure includes a voltage generation circuit connected to a power supply through a diode and having a variable resistor, the voltage generation circuit outputting a voltage corresponding to a current flowing through the diode and a resistance value of the variable resistor, as a threshold value; a comparator for comparing an analog signal inputted from a detector for detecting rotation of a motor with the threshold value inputted from the voltage generation circuit, and outputting a comparison result as a comparator output; an A/D converter for converting the analog signal into a digital signal; a threshold value determination circuit for calculating a new threshold value using the digital signal; and a resistance value change circuit for changing a resistance value of the variable resistor, such that the calculated new threshold value is inputted from the voltage generation circuit to the comparator.

Abstract: The present invention concerns a system comprising a multi-die power module composed of dies and a controller receiving plural consecutive input patterns for activating the dies of the multi-die power module, wherein the dies are grouped into plural groups of at least one die and in that the controller comprises: —means for outputting one gate to source signal for each group of at least one die, the rising edges and/or falling edges of at least one gate to source signal being iteratively time shifted from the rising edge and/or a falling edge of the other gate to source signals for other groups of dies.

Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: A power converter for converting input power to output power includes a first transformer circuit, a second transformer circuit, and balance circuitry. The first transformer circuit includes a first primary winding for receiving a first part of the input power and a first secondary winding for generating a first part of the output power. The second transformer circuit includes a second primary winding for receiving a second part of the input power and a second secondary winding for generating a second part of the output power. The balance circuitry is coupled to a first terminal of the first secondary winding and a second terminal of the second secondary winding, and operable for balancing the first and second parts of the output power by passing a signal between the first and second terminals. The first and second terminals have the same polarity.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: A voltage detector for detecting whether an input voltage is no lower than a predetermined threshold voltage, includes a reference voltage generator configured to generate a reference voltage, and a comparator configured to receive the input voltage and the reference voltage and to detect whether the input voltage is no lower than the threshold voltage that is determined by the reference voltage. Here, the reference voltage generator includes a first write MOS transistor, a second write MOS transistor, a first output MOS transistor and a second output MOS transistor each including a control gate and a floating gate.

Abstract: According to one embodiment, a neuron learning type integrated circuit device includes neuron cell units. Each of the neuron cell units includes synapse circuit units, and a soma circuit unit connected to the synapse circuit units. Each of the synapse circuit units includes a first transistor including a first terminal, a second terminal, and a first control terminal, a second transistor including a third terminal, a fourth terminal, and a second control terminal, a first condenser, one end of the first condenser being connected between the second and third terminals, and a control line connected to the first and second control terminals. The soma circuit unit includes a Zener diode including an input terminal and an output terminal, the input terminal being connected to the fourth terminal, and a second condenser, one end of the second condenser being connected between the fourth terminal and the input terminal.

Abstract: Various embodiments include an integrated circuit (IC) structure having: a chip control logic; a chip power system connected with the chip control logic; and a voltage island connected with the chip control logic and the chip power system, the voltage island including: an interface component for interfacing with the chip power system and the chip control logic; a logic island connected with the interface component; and a voltage island power system connected with the interface component and the logic island, the voltage island power system independently controlling a voltage supplied to the logic island.

Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.

Abstract: A flexible display panel includes a first display region that is flat, second display regions located at both sides of the first display region and curved by a predetermined angle, a plurality of pixels formed in the first display region, and a plurality of pixels formed in the second display regions, Each of the plurality of pixels formed in the first display region and the second display regions includes a light-emitting diode and a driving thin-film transistor (TFT) connected to the light-emitting diode, the driving TFT supplying a driving current to the light-emitting diode. A size of the driving TFT varies for each of the plurality of pixels formed in the second display regions so that driving currents supplied by driving TFTs in the second display regions vary in one direction with respect to boundaries between the first display region and the second display regions.

Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.

Abstract: A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a semiconductor substrate, a first gate insulating film having a first high-dielectric-constant insulating film containing a first metal for adjustment, and a first electrode formed on the first gate insulating film. A protrusion amount of one end of the first high-dielectric-constant insulating film on the first device isolation part is smaller than a protrusion amount of an end of the first gate electrode above the first device isolation part.

Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.