Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.

Abstract: A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.

Abstract: A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

Abstract: A method of operating a memory device, the method including matching a voltage of a selected word line, among word lines coupled to the plurality of memory cells, with a voltage of unselected word lines. The method including precharging a channel region of the plurality of memory cell strings through the common source line while discharging the selected word line and the unselected word lines.

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract: A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: An electronic device including at least first and second transistors integrated together on a substrate and each including an organic semiconductor region, wherein the first and second transistors are either both n-type or both p-type but wherein one of the first and second transistors is a normally-ON transistor and the other of the first and second transistors is a normally-OFF transistor.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers may be directly over a dummy well.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: An organic light emitting display device includes a substrate, a plurality of sub-pixels on the substrate, each sub-pixel including a first region configured to emit light and a second region configured to transmit external light, a plurality of thin film transistors disposed in the first region of the each sub-pixel, a plurality of first electrodes disposed in the first region of each sub-pixel and electrically connected to the thin film transistors, a first insulating layer on at least a portion of the first region of each sub-pixel to cover a portion of the first electrode, an organic emission layer on the first electrode, a second insulating layer on at least a portion of the second region of each sub-pixel, the second insulating layer including a plurality of openings therein, and a second electrode covering the organic emission layer, the first insulating layer, and the second insulating layer.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.

Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

Abstract: Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.

Abstract: Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins.

Abstract: In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.

Abstract: A complementary tunneling field effect transistor and a method for forming the same are provided. The complementary tunneling field effect transistor comprises: a substrate; an insulating layer, formed on the substrate; a first semiconductor layer, formed on the insulating layer and comprising first and second doped regions; a first type TFET vertical structure formed on a first part of the first doped region and a second type TFET vertical structure formed on a first part of the second doped region, in which a second part of the first doped region is connected with a second part of the second doped region and a connecting portion between the second part of the first doped region and the second part of the second doped region is used as a drain output; and a U-shaped gate structure, formed between the first type TFET vertical structure and the second type TFET vertical structure.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.

Abstract: A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.

Abstract: A semiconductor device includes a first transistor with a first drift zone, and a plurality of second transistors, each second transistor comprising a source region, a drain region and a gate electrode. The second transistors are electrically coupled in series to form a series circuit that is electrically coupled to the first transistor, the first and the plurality of second transistors being at least partially disposed in a semiconductor substrate including a buried doped layer, wherein the source or the drain regions of the second transistors are disposed in the buried doped layer.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: An SRAM array is formed by a plurality of FinFETs formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region. From a first cross sectional view of the SRAM array, each fin line is of a rectangular shape. From a second cross sectional view of the SRAM array, the terminals of each fin line is of a tapered shape.

Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

Abstract: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first portion directly over the deep well region and a second portion directly under the deep well region. A transmission line is directly over the depletion region.

Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress.

Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Abstract: There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.

Abstract: A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate.

Abstract: A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.

Abstract: When forming sophisticated gate electrode structures of transistor elements of different type, the threshold adjusting channel semiconductor alloy may be provided prior to forming isolation structures, thereby achieving superior uniformity of the threshold adjusting material. Consequently, threshold variability on a local and global scale of P-channel transistors may be significantly reduced.

Abstract: A semiconductor device having an MOSFET serving as an element to be protected, and an electrostatic protection MOSFET element mounted on the same substrate is produced with the small number of steps while implementing a high protection ability. Low concentration regions and gate electrodes are formed and then an insulation film is formed on a whole surface. Then, etching is performed using a resist pattern as a mask to leave the insulation film in a region from a part of the gate electrode to a part of the low concentration region in each of regions A1 and A3, and on a side wall of the gate electrode in a region A2. Then, a high concentration ion implantation is performed using the gate electrodes and the insulation films as masks, and then a silicide layer is formed.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

Abstract: A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.

Abstract: An embodiment of the present invention concerns a layered epitaxial structure for enhancement/depletion PHEMT devices, an enhancement/depletion PHEMT device and a method for manufacturing an enhancement/depletion PHEMT device that finds advantageous, but not exclusive, application in the manufacturing of integrated circuits operating at millimetre-wave and microwave frequencies.

Abstract: A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes first offset sidewalls formed on side surfaces in a gate width direction of a first gate electrode, second offset sidewalls formed on side surfaces in a gate length direction and the side surfaces of the gate width direction of the first gate electrode with the first offset sidewalls being interposed between the second offset sidewalls and the first gate electrode, and first extension regions. The second MIS transistor includes third offset sidewalls formed on side surfaces in a gate length direction and a gate width direction of a second gate electrode, fourth offset sidewalls formed on the side surfaces in the gate length and width directions of the second gate electrode with the third offset sidewalls being interposed between the fourth offset sidewalls and the second gate electrode, and second extension regions.

Abstract: A semiconductor device includes a semiconductor substrate including a first driving transistor region having a first driving transistor disposed therein and a second driving transistor region having a second driving transistor disposed therein, wherein the second driving transistor is driven at a lower voltage than the first driving transistor, a first gate insulating layer formed at edges of the second driving transistor region, and a second gate insulating layer formed at a center of the second driving transistor region, wherein the first gate insulating layer is thicker than the second gate insulating layer.

Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.

Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.