Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.

Abstract: A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

Abstract: A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power supply, and a gate normally grounded. The N-type enhancement mode transistor includes a drain electrically connected to the external power supply, and a gate electrically connected to a source of the depletion mode transistor.

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

Abstract: When forming sophisticated gate electrode structures of transistor elements of different type, the threshold adjusting channel semiconductor alloy may be provided prior to forming isolation structures, thereby achieving superior uniformity of the threshold adjusting material. Consequently, threshold variability on a local and global scale of P-channel transistors may be significantly reduced.

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies.

Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract: A constant current source device with over current and over voltage protection function can be directly applied to AC power and DC power, and a method for manufacturing the constant current source device is also disclosed. The device includes a silicon substrate (1), an oxide layer (6) formed in front of the silicon substrate (1), a drain metal (2), a source metal (3) and a gate metal (4) located in front of the oxide layer (6), a P+ guard ring (50), an N+ drain region (52) and an N+ source region (53) implanted in the silicon substrate (1), a P+ substrate region (51) located in the N+ source region (53), and an N? channel region (54) connecting the N+ drain region (52) with the N+ source region (53). The drain metal (2) and the source metal (3) are separately connected with the N+ drain region (52), the N+ source region (53) and the P+ substrate region (51). The source metal (3) and the gate metal (4) are electrically connected through a connection metal (7).

Abstract: A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process.

Abstract: A semiconductor memory device has a low-resistivity semiconductor substrate on which a higher-resistivity semiconductor layer of the same conductivity type is formed. Memory cell transistors are formed in the semiconductor layer. A diffusion region, also of the same conductivity type, is formed below the memory cell transistors. The resistivity of the diffusion region is lower than the resistivity of the semiconductor layer. In the programming of data into the memory cell transistors by hot electron injection, the diffusion region reduces the voltage drop due to current flow from the part of the semiconductor layer near the memory cell transistors into the semiconductor substrate, thereby reducing unwanted elevation of the potential of the semiconductor layer.

Abstract: Fabrication of complementary first and second insulated-gate field-effect transistors (110 or 112 and 120 or 122) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material (50) for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material (130) for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (74 or 94 and 154 or 194) are subsequently defined after which source/drain zones (60, 62 or 80, 82 and 140, 142 or 160, 162) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.

Abstract: A method and structure for modulating the threshold voltage of transistor is provided. An opening for an isolation region is formed within a substrate using a masking layer. The masking layer is then pulled back from the opening, and dopants are implanted into the substrate through the exposed surface of the substrate and the sidewalls of the opening. This implantation can be tailored to modulate the threshold voltage of transistors with smaller gate widths without modulating the threshold voltage of other transistors with larger gate widths.

Abstract: A semiconductor device 100 has N-well regions 18 holding PMOS devices 110, 112 and P-type regions 14 holding NMOS devices 114, 116. Devices 110 and 114 have high thresholds and devices 112 and 116 have low thresholds. The PMOS devices are junction isolated from the substrate 10 by the N-well 18 and the NMOS devices are isolated from the substrate by the N-type layer 13. Field oxide regions 20 laterally isolate the PMOS from the NMOS devices. The high threshold CMOS devices 110, 114 connect the low threshold CMOS devices to opposite rails Vdd and Vss. A control terminal 121 turns the high threshold devices on to let the low threshold devices switch rapidly. In stand-by mode, the high threshold devices are off and there is very low leakage current.

Abstract: Some embodiments comprise a plurality of fins, wherein at least a first fin of the plurality of fins comprises a different fin width compared to a fin width of another fin of the plurality of fins. At least a second fin of the plurality of fins comprises a different crystal surface orientation compared to another fin of the plurality of fins.

Abstract: A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.

Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.

Abstract: A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

Abstract: Provided is a semiconductor device which includes, on the same semiconductor substrate, a first FET and a second FET higher in threshold voltage than the first FET. The first FET includes a first gate insulating film and a first gate electrode. The second FET includes a second gate insulating film and a second gate electrode. The first gate electrode, the second gate insulating film, and the second gate electrode contain at least one metal element selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ta, and W. Concentration of the at least one metal element at an interface between the second gate insulating film and the second gate electrode in the second FET is higher than concentration of the at least one metal element at an interface between the first gate insulating film and the first gate electrode in the first FET.

Abstract: A transistor, a semiconductor device including the transistor and methods of manufacturing the same are provided, the transistor including a threshold voltage adjusting layer contacting a channel layer. A source electrode and a drain electrode contacting may be formed opposing ends of the channel layer. A gate electrode separated from the channel layer may be formed. A gate insulating layer may be formed between the channel layer and the gate electrode.

Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.

Abstract: Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed.

Abstract: In an LCD driver IC, a high-breakdown-voltage MISFET is mounted together with a typical low-breakdown-voltage MISFET. Because the high-breakdown-voltage MISFET has a gate oxide film thicker than that of the typical MISFET, the electrode of the high-breakdown-voltage MISFET is inevitably high in level. Accordingly, the depth of a gate contact is shallow so that process compatibility with the typical portion is necessary. In the present invention, in, e.g., the channel width direction of the high-breakdown-voltage MISFET, the boundary of a thick-film gate oxide region is located inwardly of the end of a gate electrode. At the gate electrode portion thus lowered in level, a gate contact is disposed so that the boundary of the thick film is located inwardly of the end of the gate electrode and between the gate contact and a channel end.

Abstract: A semiconductor device with a high-voltage transistor and a low-voltage transistor includes an isolation insulating film between a first element region of the high-voltage transistor and a second element region of the low-voltage transistor, a first gate insulating film on a semiconductor substrate in the first element region, a first gate electrode on the first gate insulating film, a second gate insulating film on the semiconductor substrate in the second element region, and a second gate electrode on the second gate insulating film. The isolation insulating film includes a first isolation region adjacent to a surrounding area of the first element region and a second isolation region adjacent to a surrounding area of the second element region. A bottom of the second isolation region is lower than a bottom of the first isolation region. The first gate insulating film is thicker than the second gate insulating film.

Abstract: A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.

Abstract: A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness.

Abstract: In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars.

Abstract: Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

Abstract: In a high-voltage NMOS transistor with low threshold voltage, it is proposed to realize the body doping that defines the channel region in the form of a deep p-well, and to arrange an additional shallow p-doping as a channel stopper on the transistor head, wherein this additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

Abstract: A semiconductor structure having: a III-V substrate structure; an enhancement mode transistor device disposed in a first region of the structure; a depletion mode transistor device disposed in a laterally displaced second region of the structure; and a RF/microwave/milli-meter wave transistor device formed in a laterally displaced third region thereof.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising first and second transistor regions that are isolated by an element isolation region; a first impurity diffusion suppression layer formed on the semiconductor substrate in the first transistor region; a second impurity diffusion suppression layer formed on the semiconductor substrate in the second transistor region, and having a thickness larger than that of the first impurity diffusion suppression layer; a first crystal layer formed on the first impurity diffusion suppression layer; a second crystal layer formed on the second impurity diffusion suppression layer; a first gate electrode formed on the first crystal layer via a first gate insulating film; a second gate electrode formed on the second crystal layer via a second gate insulating film; a first channel region formed in a region in the semiconductor substrate, the first impurity diffusion suppression layer and the first crystal layer below the first gate

Abstract: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode.

Abstract: A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer.

Abstract: There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a fully depleted MOS transistor including a first gate electrode comprising at least one type of crystalline phase selected from the group consisting of a WSi2 crystalline phase, an MoSi2 crystalline phase, an NiSi crystalline phase, and an NiSi2 crystalline phase as silicide region (1). The nMOS transistor is a fully depleted MOS transistor comprising at least one type of crystalline phase selected from the group consisting of a PtSi crystalline phase, a Pt2Si crystalline phase, an IrSi crystalline phase, an Ni2Si crystalline phase, and an Ni3Si crystalline phase as silicide region (2).

Abstract: A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier film 20 formed at least partially on the second gate-insulating film 14b, the second gate-insulating film having a lower nitrogen atom concentration than the first gate-insulating film.

Abstract: Fabrication of two differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) entails introducing multiple body-material semiconductor dopants of the same conductivity type into a semiconductor body. Gate electrodes (74 or 94) are defined such that each body-material dopant reaches a maximum concentration below the channel surface depletion regions, below all gate-electrode material overlying the channel zones (64 or 84), and at a different depth than each other body-material dopant. The transistors are provided with source/drain zones (60 or 80) of opposite conductivity type to, and with halo pocket portions of the same conductivity type as, the body-material dopants. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract: A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region.

Abstract: A semiconductor device facilitates securing a high breakdown voltage and reducing a chip area thereof includes a low-potential gate driver circuit disposed on a semiconductor substrate, a high-breakdown-voltage junction edge-termination structure disposed in a peripheral portion of a high-potential gate driver circuit, disposed on the semiconductor substrate, for separating the low-potential gate driver circuit and the high-potential gate driver circuit from each other. A trench is disposed in the edge termination structure and between an n+-type source layer and an n+-type drain layer in a level shift circuit in the high-potential gate driver circuit, and an oxide film fills the trench to form a dielectric region in trench.

Abstract: A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

Abstract: Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.

Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.

Abstract: A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.

Abstract: A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.

Abstract: A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern.