Storage Electrode Stacked Over The Transistor Patents (Class 257/E27.086)
  • Patent number: 11074964
    Abstract: Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes one or more first equalization transistors proximate the first and second regions, and includes a second equalization transistor proximate the SENSE AMPLIFIER circuitry. Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes an electrical connection coupling the first and second regions to one another.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Jiyun Li
  • Patent number: 9595528
    Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masahiko Takeuchi
  • Patent number: 9305608
    Abstract: A memory device may including a first local bit line electrically connected with a first memory cell, a first global bit line electrically connected with the first local bit line, a second local bit line electrically connected with a second memory cell, and a second global bit line electrically connected with the second local bit line. The first global bit line is primarily charged with electric charge. The first global bit line and the second global bit line share the primarily charged electric charge. The second global bit line is secondarily charged with the electric charge.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Kook Park
  • Patent number: 8981453
    Abstract: A nonvolatile memory device includes a unit cell with a transistor and a capacitor. The transistor is disposed on a substrate having a tunneling region and a channel region and includes a floating gate crossing both the tunneling region and the channel region. The capacitor is coupled to the floating gate.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: March 17, 2015
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jae-han Cha
  • Patent number: 8890224
    Abstract: A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A metal-insulator-metal (MIM) capacitor structure is disposed over the substrate. A dual damascene structure disposed over and electrically coupled with the TSV structure, wherein the dual damascene structure includes a via portion and a trench portion A first dielectric layer is disposed around the via portion of the dual damascene structure. A second dielectric layer disposed around the trench portion of the dual damascene, wherein the second dielectric layer is disposed over the MIM capacitor structure.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Sung-Hui Huang, Der-Chyang Yeh
  • Patent number: 8766345
    Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Shu-Jen Han, George S. Tulevski
  • Patent number: 8748962
    Abstract: A semiconductor device includes a capacitor dielectric film formed on a lower electrode and made of a ferroelectric material, and an upper electrode formed on a capacitor dielectric film, wherein the lower electrode includes a lowest conductive layer and an upper conductive layer, the lowest conductive layer being made of a noble metal other than iridium, and the upper conductive layer being formed on the lowest conductive layer and made of a conductive material, which is different from a material for the lowest conductive layer, and which is other than platinum.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: June 10, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8716778
    Abstract: Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Jeffrey T. Watt, Mojy Curtis Chian
  • Patent number: 8710569
    Abstract: A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Inoue, Masayuki Hamada
  • Patent number: 8686486
    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito
  • Patent number: 8552485
    Abstract: A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Sung-Hui Huang, Der-Chyang Yeh
  • Patent number: 8541827
    Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshitake Yaegashi
  • Patent number: 8476687
    Abstract: Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: July 2, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Vijay B. Rentala, Srinath M. Ramaswamy, Baher S. Haroun, Eungyoung Seok
  • Patent number: 8426269
    Abstract: A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: April 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Baek-Mann Kim
  • Patent number: 8350307
    Abstract: Provided is a semiconductor memory device including a capacitor structure extending over core and peripheral areas of a substrate. Respective portions of the capacitor structure function as memory cell capacitors in the core area and as first and second capacitors in the peripheral area. A combination of the first and second capacitors functions as a first power decoupling capacitor, and a transistor disposed in the peripheral area functions as a second power decoupling capacitor.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sunghoon Kim
  • Patent number: 8324674
    Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshitake Yaegashi
  • Patent number: 8309999
    Abstract: The method includes the steps of forming an upper electrode of a capacitor by patterning a second conductive film; forming a capacitor dielectric film by patterning a ferroelectric film; and forming a lower electrode by patterning a first conductive film. A step of forming the first conductive film includes the steps of forming a lower conductive layer made of a noble metal other than iridium over a first interlayer insulating film; and forming an upper conductive layer made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 13, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8309416
    Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Shil Park, Yong-Seok Eun, Kee-Jeung Lee, Min-Soo Kim
  • Publication number: 20120193697
    Abstract: A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F2, or when a special structure is employed for a cell transistor, an area per memory cell less than or equal to 4F2 can be achieved.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 2, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yasuhiko TAKEMURA
  • Patent number: 8212298
    Abstract: A semiconductor storage device where one MOS transistor in a memory cell section includes a selection transistor, and one MOS transistor in a peripheral circuit section includes a first MOS transistor and a second MOS transistor of different conductivity type, the first MOS and second MOS transistors and the selection transistor include lower drain or source regions in a planar semiconductor layer, a pillar-shaped semiconductor layer on the planar semiconductor layer, upper source or drain regions in an upper portion of the pillar-shaped semiconductor layer, and a gate electrode that surrounds a sidewall of the pillar-shaped semiconductor layer through a dielectric film, and where a first silicide layer connects a surface of the lower drain or source region of the first MOS and second MOS transistors, and a second silicide layer on a surface of the lower drain or source region of the selection transistor.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: July 3, 2012
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Shintaro Arai
  • Patent number: 8203204
    Abstract: A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 19, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 8188529
    Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: May 29, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
  • Patent number: 8183614
    Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 22, 2012
    Assignee: Nanya Technology Corporation
    Inventor: Shin-Yu Nieh
  • Publication number: 20120119276
    Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
  • Publication number: 20120119277
    Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
  • Patent number: 8159016
    Abstract: A capacitor of a semiconductor device, and a method of manufacturing the capacitor of the semiconductor device, include a lower electrode layer, a dielectric layer, and an upper electrode layer, wherein the dielectric layer includes tantalum (Ta) oxide and an oxide of a Group 5 element, such as niobium (Nb) or vanadium (V).
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Park, Jung-hyun Lee
  • Publication number: 20120086066
    Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.
    Type: Application
    Filed: April 29, 2011
    Publication date: April 12, 2012
    Inventors: Daeik KIM, HyeongSun HONG, Yoosang HWANG, Hyun-Woo CHUNG
  • Patent number: 8148764
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Ho Jin Cho, Dong Kyun Lee
  • Patent number: 8101986
    Abstract: In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions (10) and the gate surfaces (6) of transistors in the DRAM section and the logic section, concurrently in one and the same step.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Inoue, Masayuki Hamada
  • Patent number: 8084804
    Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: December 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-jeung Lee
  • Patent number: 8080471
    Abstract: Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: December 20, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhon Jhy Liaw, Yu-Jen Wang, Chia-Shiung Tsai
  • Patent number: 8053822
    Abstract: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Young-gu Jin, Yoon-dong Park
  • Patent number: 8013377
    Abstract: Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: September 6, 2011
    Assignee: Qimonda AG
    Inventors: Peter Baars, Stefan Tegen, Klaus Muemmler
  • Patent number: 7985999
    Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Oh, Jeong-Nam Han, Chang-Ki Hong, Woo-Gwan Shim, Im-Soo Park
  • Publication number: 20110127596
    Abstract: A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
    Type: Application
    Filed: February 11, 2011
    Publication date: June 2, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Howard C. Kirsch, Charles Ingalls, Werner Juengling
  • Patent number: 7952133
    Abstract: Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating the insulation layer on one side of the stacked gate; and a source line penetrating the insulation layer on an opposite side of the stacked gate.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: May 31, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Woo Nam
  • Publication number: 20110073925
    Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.
    Type: Application
    Filed: December 30, 2009
    Publication date: March 31, 2011
    Inventors: Eun-Shil PARK, Young-Seok Eun, Kee-Jeung Lee, Min-Soo Kim
  • Patent number: 7893476
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: February 22, 2011
    Assignee: IMEC
    Inventor: Anne S. Verhulst
  • Patent number: 7884410
    Abstract: Example embodiments may provide nonvolatile memory devices and example methods of fabricating nonvolatile memory devices. Example embodiment nonvolatile memory devices may include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-wook Moon, Joong S. Jeon, El Mostafa Bourim, Hyun-deok Yang
  • Patent number: 7880213
    Abstract: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: February 1, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Miao Lo, Lurng-Sheng Lee, Pei-Ren Jeng, Cha-Hsin Lin, Ching-Chiun Wang
  • Patent number: 7872250
    Abstract: A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between the top electrode and the bottom electrode.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: January 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-mock Lee, Jin-heong Yim, Yoon-ho Khang, Jin-seo Noh, Dong-seok Suh
  • Patent number: 7851843
    Abstract: A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 14, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Yuan Lee, Chieh-Shuo Liang, Lurng-Shehng Lee
  • Patent number: 7847384
    Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: December 7, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tsuyoshi Kobayashi, Tetsuya Koyama, Takaharu Yamano
  • Patent number: 7825451
    Abstract: The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventor: H. Montgomery Manning
  • Patent number: 7825450
    Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Walker, Karl M. Robinson
  • Patent number: 7812386
    Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshitake Yaegashi
  • Patent number: 7811880
    Abstract: A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask is positioned at a second position relative to the substrate, and a second material layer is formed above the first material layer based on the pattern on the photo mask, the second material layer being offset from the first material layer so that a first sub-cell of the memory cell includes the first material layer and not the second material layer, and a second sub-cell of the memory cell includes both the first and second material layers. A second electrode is formed above the first and second material layers.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: October 12, 2010
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventor: Geoffrey Wen-Tai Shuy
  • Patent number: 7795662
    Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideyuki Arai, Takashi Nakabayashi
  • Patent number: 7786523
    Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 31, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
  • Patent number: 7745867
    Abstract: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston