Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: The present application relates to semiconductor structure and forming method comprising: forming substrate, wherein plurality of capacitive contacts are provided in the substrate, plurality of electrically conductive contact pads are provided at surface of the substrate to be correspondingly connected to plurality of capacitive contacts on one-to-one basis, and a space is present between every two adjacent electrically conductive contact pads; forming filling layer that is fully filled in the space; forming stacked structure at the filling layer and surface of the electrically conductive contact pads, wherein the stacked structure includes plurality of supporting layers stacked one-on-another along direction perpendicular to the substrate, the filling layer is in contact with the supporting layer disposed at bottom of the stacked structure, and etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than preset value; and etching the stacked structure to for

Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.

Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Abstract: An array substrate includes an insulation layer and one or more stepped holes each penetrating through the insulation layer in a direction perpendicular to the insulation layer. Each stepped hole includes a first hole and a second hole under the first hole, a radius of the first hole at a bottom is a first radius, a radius of the second hole at a top is a second radius which is substantially smaller than the first radius, and a difference between the first radius and the second radius is 0.2 ?m to 0.6 ?m.

Abstract: Disclosed are a touch display panel, a driving circuit and a driving method of a touch display panel. The touch display panel includes a common electrode layer which used for display. The common electrode layer is also used as a touch detection electrode layer for touch detection. The common electrode layer is divided into a number of regions, which are respectively connected to the same number of selectors that are each connected to each of the same number of common voltage generating circuits to receive the same number of common voltages and selectively transmit the common voltages to the plurality of regions.

Abstract: A semiconductor device includes a substrate with cell and peripheral regions and capacitors provided on the cell region. The cell region may include a plurality of sub-cell blocks, which are spaced apart from each other by a plurality of sub-peripheral regions, and on which the capacitors are provided. Each of the sub-peripheral regions may have a width that is two to five times a distance between centers of an adjacent pair of the capacitors.

Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.

Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.

Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

Abstract: A semiconductor device includes a semiconductor substrate having a first groove, a word line in the first groove, and a buried insulating film in the first groove. The buried insulating film covers the word line. The buried insulating film comprises a silicon nitride film.

Abstract: A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.

Abstract: Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line.

Abstract: In a semiconductor device, a polysilicon layer of a lower electrode contact plug is removed by a strip process such that the deposition area of a dielectric film is increased and capacitance of a capacitor is assured. A method for manufacturing the semiconductor device is also disclosed.

Abstract: Semiconductor devices including spacers on sidewalls of conductive lines are provided. The semiconductor device includes bit lines on a semiconductor substrate, a storage node contact plug penetrating an insulation layer between the bit lines, triple-layered bit line spacers between the bit lines and the storage node contact plugs, and storage node electrodes on the storage node contact plugs. Each of the triple-layered bit line spacers includes a first spacer adjacent to one of the bit lines, a third spacer adjacent to the storage node contact plugs and a second spacer between the first and third spacers. The second spacer includes a lower portion having a lower dielectric constant than the first and third spacers and an upper portion having the same material as the first and third spacers. Related methods are also provided.

Abstract: A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.

Abstract: The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions. The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.

Abstract: Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field.

Abstract: A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region; a bit line extending over the memory cell region and the peripheral circuit region, the bit line including a first portion in the peripheral circuit region; and a sense amplifier in the peripheral circuit region. The sense amplifier includes a transistor having a gate electrode which includes the first portion of the bit line.

Abstract: A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.

Abstract: A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors. The pillars are aligned in a straight line in a first direction and have respectively a primary control wall along the first direction and two ancillary control walls perpendicular to the primary control wall. The gate line is connected to the primary control wall in the first direction through a first isolated layer. The conductors are interposed between the ancillary control walls through second isolated layers. By providing the gate line merely on the primary control wall and the conductors to aid the gate line to control ON/OFF of the pillars, problems of etching and separating gate material during gradually shrunken feature size process that are difficult to control etching positions and etching duration can be prevented.

Abstract: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.

Abstract: Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns.

Abstract: Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.

Abstract: A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.

Abstract: A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors. The pillars are aligned in a straight line in a first direction and have respectively a primary control wall along the first direction and two ancillary control walls perpendicular to the primary control wall. The gate line is connected to the primary control wall in the first direction through a first isolated layer. The conductors are interposed between the ancillary control walls through second isolated layers. By providing the gate line merely on the primary control wall and the conductors to aid the gate line to control ON/OFF of the pillars, problems of etching and separating gate material during gradually shrunken feature size process that are difficult to control etching positions and etching duration can be prevented.

Abstract: To provide an active region having first and second diffusion layers positioned at both sides of a gate trench and a third diffusion layer formed on a bottom surface of the gate trench, first and second memory elements connected to the first and second diffusion layers, respectively, a bit line connected to the third diffusion layer, a first gate electrode that covers a first side surface of the gate trench via a gate dielectric film and forms a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode that covers a second side surface of the gate trench via a gate dielectric film and forms a channel between the second diffusion layer and the third diffusion layer. According to the present invention, because separate transistors are formed on both side surfaces of a gate trench, two times of conventional integration can be achieved.

Abstract: A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film.

Abstract: A semiconductor device having a reduced bit line parasitic capacitance and a method of making same is presented. The semiconductor device includes a first, second, third, and fourth interlayer dielectric layers, first and second bit lines, first and second landing plug and first and second storage node contacts. An optional capacitor may be added to complete a CMOS configuration for the semiconductor device. The storage node contacts traverse through the interlayer dielectric layer and are electrically coupled to their respective landing plug contacts. The storage node contacts are deliberately offset, relative to the center of the corresponding landing plug contacts, at a predetermined distance in a direction away from the first bit line. This offsetting aids reducing the parasitic capacitance between the bit line and a storage node.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Abstract: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase the area of the storage electrode formed over sacrificial layer. This process results in increasing the capacity of the capacitor in a stable manner.

Abstract: Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.

Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.

Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A memory element is formed by providing an organic compound between a pair of upper and lower electrodes. However, when the electrode is formed over a layer containing an organic compound, a temperature is limited because the layer containing the organic compound can be influenced depending on a temperature for forming the electrode. A forming method for the electrode is limited due to this limitation of a temperature. Therefore, there are problems that an expected electrode cannot be formed, and miniaturization of an element is inhibited. A semiconductor device includes a memory element and a switching element which are provided over a substrate having an insulating surface. The memory element includes first and second electrodes, and a layer containing an organic compound, which are provided on the same plane. A current flows from the first electrode to the second electrode. The first electrode is electrically connected to the switching element.

Abstract: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.

Abstract: An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external surface by an etch process that resists destructive collapse of the conductive structure.

Abstract: A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers (11, 12) provided in a lower part and an upper part, respectively of the silicon pillar, a bit line connected to the diffusion layer (11), and a memory element connected to the diffusion layer (12). The bit line includes a silicon material region in contact with the diffusion layer (11), and a low-resistance region including a material having lower electric resistance than that of the silicon material region. As a result, the resistance of the bit line embedded in the substrate can be decreased.

Abstract: A semiconductor device includes a semiconductor substrate having an active region comprising a gate area, a bit line contact area and a storage node contact area. A recess is formed in the gate area and the bit line contact area. A gate is formed over the gate area and a portion of an isolation layer adjacent to the gate area. The gate includes a main gate in the gate area and a passing gate over the isolation layer. A first junction area is formed in the storage node contact area of the active region. A second junction area is formed in the bit line contact area of the active region. A first landing plug and a second landing plug are formed over the first junction area and the second junction area, respectively.

Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

Abstract: A semiconductor device includes: a transistor having source and drain regions; first and second contact electrodes embedded in a first interlayer insulating film, and electrically connected to the source region and the drain region, respectively; a third electrode embedded in a second interlayer insulating film positioned in an upper layer of the first interlayer insulating film, and electrically connected to the first contact electrode; a wiring pattern embedded in a third interlayer insulating film positioned in an upper layer of the second interlayer insulating film, and electrically connected to the third contact electrode; and a fourth contact electrode embedded in at least the second and third interlayer insulating films, and electrically connected to the second contact electrode, wherein side surfaces of the wiring pattern along an extending direction of the wiring pattern coincide with side surfaces of the third contact electrode along an extending direction of the wiring pattern.

Abstract: The capacitor structure includes a first electrode having a plurality of teeth protruding in a comb shape from an electrode base of a first electrode line and a second electrode having a plurality of teeth protruding in a comb shape from an electrode base of a second electrode line, both formed in a first wiring layer. The first and second electrodes face each other with their teeth interdigitated with each other via a dielectric. At least one of the teeth of the first electrode is electrically connected with a third electrode line formed in a second wiring layer.

Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.