Abstract: A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method includes providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of the substrate respectively. A well region is formed in the isolation deep well simultaneously with forming an isolation well region between the isolation deep well and the deep well in the substrate. A depletion doped region and a cell implant region are formed at the well region of the substrate and the deep well of the substrate respectively. A floating gate structure is formed across over the floating region and the control region. An implantation process is performed to form a source/drain region and a heavily doped region in the depletion doped region and the cell implant region respectively.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

Abstract: In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer.

Abstract: In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film.

Abstract: A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

Abstract: A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.

Abstract: A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; and a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction.

Abstract: A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conducti

Abstract: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening.

Abstract: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.

Abstract: A method of forming gate patterns of a nonvolatile memory device comprises forming stack patterns each having an insulating layer and a conductive layer stacked over a semiconductor substrate, and forming an anti-oxidation layer on sidewalls of the insulating layer by selectively nitrifying the insulating layer.

Abstract: A semiconductor device including a semiconductor substrate having an active region isolated by an element isolation insulating film; a floating gate electrode film formed on a gate insulating film residing on the active region; an interelectrode insulating film formed above an upper surface of the element isolation insulating film and an upper surface and sidewalls of the floating gate electrode film, the interelectrode insulating film being configured by multiple film layers including a high dielectric film having a dielectric constant equal to or greater than a silicon nitride film; a control gate electrode film formed on the interelectrode insulating film; and a silicon oxide film formed between the upper surface of the floating gate electrode film and the interelectrode insulating film; wherein the high dielectric film of the interelectrode insulating film is placed in direct contact with the sidewalls of the floating gate electrode film.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility.

Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

Abstract: A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

Abstract: A semiconductor device includes a semiconductor element and a protection diode formed on a semiconductor substrate. Over the semiconductor substrate, a first interlayer dielectric layer is formed so as to cover the semiconductor element and the protection diode. In the first interlayer dielectric layer, a first plug electrically connected to the semiconductor element and a second plug electrically connected to the protection diode are formed. The area of the top surface of the second plug is greater than the area of the top surface of the first plug.

Abstract: A nonvolatile memory element comprises a resistance variable element 105 configured to reversibly change between a low-resistance state and a high-resistance state in response to electric signals with different polarities which are applied thereto; and a current controlling element 112 configured such that when a current flowing when a voltage whose absolute value is a first value as a desired value which is larger than 0 and smaller than a predetermined voltage value and whose polarity is a first polarity is applied is a first current and a current flowing when a voltage whose absolute value is the first value and whose polarity is a second polarity different from the first polarity is applied is a second current, the first current is higher than the second current, and the resistance variable element is connected in series with the current controlling element such that a polarity of a voltage applied to the current controlling element when the resistance variable element is changed from the low-resistance s

Abstract: A nonvolatile semiconductor memory device includes the following structure. Element isolation films are formed at predetermined intervals in a first direction in a surface region of a semiconductor substrate. The element isolation films extend in a second direction and isolate the surface region of the semiconductor substrate to provide element regions. Upper surface of the element isolation films are lower than upper surface of the element regions of the semiconductor substrate. A tunnel insulating film is formed on the element region. A charge accumulation layer is formed only on the tunnel insulating film. A block layer continuously is formed in the first direction on the charge accumulation layer and the element isolation film. A bottom surface of the block layer on the element isolation film is lower than the upper surface of the element region of the semiconductor substrate. A gate electrode is formed on the block layer.

Abstract: A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolatio

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.

Abstract: A nonvolatile semiconductor memory device includes a plurality of bit line diffusion layers formed in a semiconductor region, and extending in a row direction; a plurality of first insulating films, each being formed on the semiconductor region and between adjacent two of the bit line diffusion layers, and including a charge trapping film; a plurality of bit line insulating films formed above the respective bit line diffusion layers; and a plurality of word lines formed above the semiconductor region to cover the first insulating films and the bit line insulating films, intersecting the bit line diffusion layers, and extending in a column direction. The bit line insulating films have smaller thicknesses than the first insulating films, and upper surfaces of the bit line insulating films are parallel to upper surfaces of the first insulating films.

Abstract: A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).

Abstract: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.

Abstract: A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region.

Abstract: A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.

Abstract: A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

Abstract: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction.

Abstract: A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first conductive region and the second conductive region.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.

Abstract: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed around the charge storage film; an electrode extending two-dimensionally to surround the charge storage insulating film, the electrode having a groove; and a metal silicide formed on a sidewall of the groove.

Abstract: A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction.

Abstract: Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a cell gate-conductive film are provided on the cell field region of the substrate including the device isolation films. A high-voltage gate-insulation film and a high-voltage gate-conductive film are provided on the high-voltage field region of the substrate including the device isolation films. The device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein.

Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.

Abstract: A method is provided for fabricating a semiconductor device having a gate electrode overlying a gate insulator. The method, in accordance with one embodiment, comprises depositing a layer of spin on glass overlying the gate electrode, the layer of spin on glass comprising a substantially UV opaque material. The layer of spin on glass is heated to a temperature less than about 450° C., and all subsequent process steps in the fabrication of the device are limited to temperatures less than about 450° C.

Abstract: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

Abstract: A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask is positioned at a second position relative to the substrate, and a second material layer is formed above the first material layer based on the pattern on the photo mask, the second material layer being offset from the first material layer so that a first sub-cell of the memory cell includes the first material layer and not the second material layer, and a second sub-cell of the memory cell includes both the first and second material layers. A second electrode is formed above the first and second material layers.

Abstract: Disclosed herein is a storage element including: a first electrode; a second electrode formed in a position opposed to the first electrode; and a variable-resistance layer formed so as to be interposed between the first electrode and the second electrode. The first electrode is a tubular object, and is formed so as to be thicker on an opposite side from the variable-resistance layer than on a side of the variable-resistance layer.

Abstract: A non-volatile memory devices includes: a substrate including a circuit device and a metal line electrically connected with the circuit device; a diode connected with the metal line in a vertical direction with respect to a surface of the substrate, and including a metal layer disposed on a lower part of the diode facing the surface of the substrate; and a resistor electrically connected with the diode in series.

Abstract: Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top surface of the plurality of layer, the first plurality of pitch-multiplied spacers being above the central region of the substrate, and a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary.

Abstract: The present invention provides a semiconductor memory device having a capacitor electrode of a MOS capacitor formed in polygon and slanting faces enlarged toward an insulating film are provided therearound. A floating gate electrode is provided which extends from over a channel region of a MOSEFT to over corners of ends on the MOSFET side, of the capacitor electrode and which is opposite to the channel region and the capacitor electrode with a gate insulating film interposed therebetween.

Abstract: Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application.

Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.

Abstract: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.