Abstract: A ferromagnetic thin-film based digital memory having a substrate formed of a base supporting an electrically insulating material primary substrate layer in turn supporting a plurality of current control devices each having an interconnection arrangement with each of said plurality of current control devices being separated from one another by spacer material therebetween and being electrically interconnected with information storage and retrieval circuitry. A plurality of bit structures are each supported on and electrically connected to a said interconnection arrangement of a corresponding one of said plurality of current control devices and have magnetic material films in which a characteristic magnetic property is substantially maintained below an associated critical temperature above which such magnetic property is not maintained of which two are separated by at least one intermediate layer of a nonmagnetic material having two major surfaces on opposite sides thereof.

Abstract: A ferroelectric capacitor and a method for manufacturing the same includes a lower electrode, a dielectric layer, and an upper electrode layer, which are sequentially stacked, wherein the dielectric layer has a multi-layer structure including a plurality of sequentially stacked ferroelectric films, and wherein two adjacent ferroelectric films have either different compositions or different composition ratios. Use of a ferroelectric capacitor according to an embodiment of the present invention, it is possible to hold stable polarization states of ferroelectric domains for a long retention time, and thus data written in the ferroelectric capacitor a long time ago can be accurately written, thereby improving the reliability of a ferroelectric random access memory (FRAM).

Abstract: A semiconductor memory device includes a cell block composed of several series-connected units having a ferroelectric capacitor and a cell transistor parallel-connected to the ferroelectric capacitor and a select transistor connected to an end of the cell block. Mutually separated first impurity diffusion layers are formed on the surface of the semiconductor substrate along a first direction, and have a first area. A second impurity diffusion layer is formed on the surface of the semiconductor substrate separated from the end first impurity diffusion layer, and has a second area. A first gate electrode is provided on the semiconductor substrate between the first impurity diffusion layers along a second direction. A second gate electrode is provided on the semiconductor substrate between the end first impurity diffusion layer and the second impurity diffusion layer along a second direction. A contact electrically connects a bit line and the second impurity diffusion layer.

Abstract: A nonvolatile memory cell, a memory device and a corresponding production method are disclosed. In one embodiment, a memory material region is in this case provided as memory element between a first electrode device and a second electrode device. The memory material region can be activated by means of at least one species. The memory material region is formed with or from a nanostructure.

Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

Abstract: A method of manufacturing a semiconductor device is provided including: forming a groove in an insulation film; forming a lower electrode material film on the insulation film and in the groove; forming a ferroelectric material film on the lower electrode material film, on the insulation film and in the groove; forming an upper electrode material film on the ferroelectric material film, on the insulation film and in the groove; forming a capacitive element within the groove by removing the upper electrode material film and the ferroelectric material film from the insulation film and leaving the upper electrode material film and the ferroelectric material film within the groove by CMP-polishing the insulation film and the groove.

Abstract: An amorphous high-k thin film for a semiconductor device and a manufacturing method thereof are provided. The amorphous high-k thin film includes Bi, Ti, Al, and O. Since a BTAO based amorphous dielectric thin film is used as a dielectric material of a DRAM capacitor, a dielectric constant is more than 25, and an increase of a leakage current caused in reducing a physical thickness of the dielectric thin film can be prevented. Accordingly, it is very useful for the integration of the semiconductor device.

Abstract: The capacitor is a thin-film capacitor comprising two metal electrodes separated by a dielectric. The dielectric is formed by superposition of at least two sub-layers of preferably perovskite-based dielectric material. Two adjacent superposed dielectric sub-layers are separated by an electrically insulated metal intermediate layer, for example made of platinum. Using very thin dielectric sub-layers, preferably with a thickness of less than 20 nm, separated from one another by metal intermediate layers enables the increase of the breakdown field and the reduction of the leakage currents linked to a reduction of the thickness of the dielectric to be transposed to the level of the capacitor, while preserving a reasonable working field.

Abstract: The invention relates to a memory element comprised of an electrode (2), of a ferroelectric layer (3), which is adjacent thereto, of a layer (4), which is made of a non-ferroelectric material and which is adjacent to said ferroelectric layer (3), and of an electrode (5), which is made of a non-ferroelectric material and which is adjacent to layer (4). The electric resistance of the ferroelectric layer and of the non-ferroelectric layer are preferably low. The invention also relates to a method for electronically storing information by writing an item of information into a memory element of the aforementioned type by aligning a polarization in a polarizable layer, and the information is read by determining the polarizing direction by measuring resistance. This renders a particularly fast remanent storage of electronic data possible.

Abstract: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold switching characteristics. The nonvolatile semiconductor memory device may include a lower electrode; a first resistance layer having at least two resistance characteristics formed on the lower electrode, a second resistance layer having threshold switching characteristics formed on the first resistance layer, and an upper electrode formed on the second resistance layer.

Abstract: A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines and barrier layers. Such structures are then exposed to the high temperature processing steps and should be resistant to such temperatures.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

Abstract: A memory cell array is provided that includes ferroelectric capacitors with enhanced characteristics, a method of making the same, and a ferroelectric memory device including the memory cell. In a memory cell array, memory cells including ferroelectric capacitors are arrayed in a matrix. Each ferroelectric capacitor includes a lower electrode, an upper electrode, and a ferroelectric section disposed between the lower electrode and the upper electrode. The ferroelectric section is disposed in an intersection between the lower electrode and the upper electrode. An intermediate electrode is disposed between the ferroelectric section 14 and the upper electrode.

Abstract: A ferroelectric memory includes a substrate and a sheet-shaped device formed over the substrate through an adhesive layer. The sheet-shaped device includes a memory cell array in which a ferroelectric layer is disposed at least in intersecting regions of a plurality of lower electrodes and a plurality of upper electrodes which are formed in the shape of lines, and a peripheral circuit section for the memory cell array.

Abstract: The present invention is related to a ferroelectric memory device and a method for fabricating the same. The ferroelectric memory device includes: a substrate providing a transistor; a first insulation material with a plane surface formed on the substrate; a storage node contact passing through the first insulation material to contact to an active region of the substrate; a lower electrode being connected to the storage node contact and including a solid solution layer disposed at least as an upper most layer, the solid solution layer being doped with a metal element, which is induced to be in a solid solution state; a second insulation material having a plane surface that exposes a surface of the lower electrode, encompassing the lower electrode and being formed on the first insulation material; a ferroelectric layer covering the second insulation material including the lower electrode; an upper electrode formed on the ferroelectric layer.

Abstract: In a semiconductor memory device having a capacitor layer comprising a dielectric film or a ferroelectric film, as an interlayer insulation film formed between the capacitor and a wiring layer formed at the upper part thereof or an insulation film which covers the wiring layer, a multilayered film is used which consists of a first insulation film and a second insulation film laid upon the other; the former being a lower layer and being formed of an organic film, and the latter being an upper layer and being formed of a hard-mask material. This makes it possible to prevent thin film comprised of a dielectric material or a ferroelectric material from any deterioration caused by the hydrogen and water contained in the interlayer insulation film and passivation film of the semiconductor memory device and also by the stress of these films.

Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.

Abstract: A thin film magnetic memory device includes: TMR elements provided at a predetermined distance away from each other on a main surface of a silicon substrate so as to operate as memory elements; a first digit line for applying a magnetic field to TMR element, extending in one direction so as to intersect TMR element; a second digit line for applying a magnetic field to TMR element, extending parallel to the first digit line so as to intersect TMR element; and a magnetic film provided so as to fill in the space between the first digit line and the second digit line and so as to bring into contact with the first and second digit lines. The present invention provides a thin film magnetic memory device wherein crosstalk can be prevented from generating between adjacent memory cells and wherein wire resistance does not increase.

Abstract: An interlayer insulating film is formed on a semiconductor substrate on which a transistor has been formed, and an adhesion layer made from a metal oxide not oriented is formed on the interlayer insulating film. A capacitor composed of a lower electrode, a capacitor dielectric film made from a high dielectric constant material or a ferroelectric material and an upper electrode successively formed in this order above the semiconductor substrate is provided on the adhesion layer. A conducting plug for electrically connecting the transistor and the capacitor to each other is provided in the interlayer insulating film and the adhesion layer.

Abstract: A first memory cell block has memory cells connected together in series. Each of the memory cells comprises a cell transistor and a ferroelectric capacitor. The ferroelectric capacitor has an electrode at one end and an electrode at the other end which are connected to a source and a drain of the cell transistor, respectively. A first metal interconnect is connected between one end of the first block and one end of a current path in a first block selection transistor. A first bit line is connected to the other end of the current path in the first transistor. A second bit line is arranged adjacent to the first bit line. Second and third block selection transistors each have a current path one end of which is connected to the second bit line. Interconnects connected to gate electrodes of the second and third transistors are disposed below the first interconnect.