Abstract: The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

Abstract: Provided is a semiconductor device containing a silicon single crystal substrate 101, a silicon carbide layer 102 provided on a surface of the substrate, a Group III nitride semiconductor junction layer 103 provided in contact with the silicon carbide layer, and a superlattice-structured layer 104 constituted by Group III nitride semiconductors on the Group III nitride semiconductor junction layer. In this semiconductor device, the silicon carbide layer is a layer of a cubic system whose lattice constant exceeds 0.436 nm and is not more than 0.460 nm and which has a nonstoichiometric composition containing silicon abundantly in terms of composition, and the Group III nitride semiconductor junction layer has a composition of AlxGaYInzN1-?M? (0?X, Y, Z?1, X+Y+Z=1, 0??<1, M is a Group V element except nitrogen).

Abstract: Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract: An array of thyristor detector devices is provided having an epitaxial growth structure with complementary types of modulation doped quantum well interfaces located between a P+ layer and an N+ layer. The thyristor detector devices operate over successive cycles that each include a sequence of two distinct modes: a setup mode and a signal acquisition mode. During the setup mode, the n-type quantum well interface and/or the p-type quantum well interface is(are) substantially emptied of charge. During the signal acquisition mode, photocurrent is generated by the thyristor detector device in response to the absorption of incident electromagnetic radiation therein, which can induce the thyristor detector device to switch from an OFF state to an ON state. The OFF/ON state of the thyristor detector device produces an output digital electrical data that corresponds to the amount of incident radiation absorbed by the thyristor detector device during the signal acquisition mode of the current cycle.

Abstract: A semiconductor epitaxial structure includes a substrate; a semiconductor epitaxial stack layers formed on the substrate; and a plurality of semiconductor buffer layers deposited between the substrate and the semiconductor epitaxial layer with a gradually varied composition along one direction; wherein more than one of the semiconductor buffer layers have a patterned surface.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer includes a carbon nanotube structure comprised of carbon nanotubes. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The carbon nanotube structure is connected to both the source electrode and the drain electrode, and an angle exist between each carbon nanotube of the carbon nanotube structure and a surface of the semiconductor layer, and the angle ranges from about 0 degrees to about 15 degrees.

Abstract: A semiconductor device may reduce a dislocation density and tensile stress by forming a plurality of interlayers between neighboring clad layers. The semiconductor device may include a plurality of clad layers on a substrate and a plurality of interlayers between neighboring clad layers.

Abstract: A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.

Abstract: Nanocrystals having an indium-based core and methods for making them and using them to construct core-shell nanocrystals are described. These core-shell nanocrystals are highly stable and provide higher quantum yields than known nanocrystals of similar composition, and they provide special advantages for certain applications because of their small size.

Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.

Abstract: The method utilises a conducting trench base with non-conducting trench walls to corral charged particles precisely into the trenches. The nanoparticles are close packed in the channels and highly ordered. This approach utilises the charge on the particles to selectively deposit them within the trenches, as all nanoparticles in solution can be charged, and this can be extended to any nanoparticle system beyond gold. Also, this method results in the layer-by-layer growth of the gold nanoparticles. Therefore the depth of the nanoparticle layers within the trenches is controllable. This allows the possibility of heterolayered structures of different nanoparticle layers. Further this method ensures that assembly occurs to fill the void space available provided the back-contacting electrode is more conducting than the trench walls.

Abstract: There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately with each other, wherein the active layer includes a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer toward the p-type nitride semiconductor layer and having a quantum level higher than a quantum level of the first quantum well layer, and a tunneling quantum barrier layer formed between the first and second quantum well layers and having a thickness enabling a carrier to be tunneled therethrough.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: Provided is a surface light emitting element having a high productivity, a high light emission output and good response characteristics, as well as capable of suppressing an increase of a forward voltage necessary for light emission. A surface light emitting element according to the present invention is a vertical cavity surface light emitting element including: an active layer 5 in which a quantum well layer 51 and a barrier layer 52 are alternately laminated; and reflective layers disposed both above and below the active layer 5, wherein assuming that a center-to-center distance of a plurality of the quantum well layers is L, a light emission wavelength of the surface light emitting element is ?, and an average refractive index of an optical length of a resonator, being a distance between the reflective layers is n, a condition of ?/(15×n)?L??/(10×n) is satisfied.

Abstract: A patterned array of metallic nanostructures and fabrication thereof is described. A device comprises a patterned array of metallic columns vertically extending from a substrate. Each metallic column is formed by metallically coating one of an array of non-metallic nanowires catalytically grown from the substrate upon a predetermined lateral pattern of seed points placed thereon according to a nanoimprinting process. An apparatus for fabricating a patterned array of metallic nanostructures is also described.

Abstract: A substrate for mounting light emitting elements having two or more conductive layers and an insulating layer provided between each conductive layer, which are formed on the outside of an enameled substrate, the enameled substrate being an enamel layer covering the surface of a core metal. The conductive layer provided on the enamel layer side links one end of enameled substrate to the other end, and feeds power to a plurality of light emitting elements mounted in the longitudinal direction of the conductive layer. Furthermore, the conductive layer on the surface of a protruding section provided at both ends of the enameled substrate extends and forms a connection with another substrate. A light emitting module is formed by mounting light emitting elements on the substrate.

Abstract: A nitride-based light emitting device capable of achieving an enhancement in light emission efficiency and an enhancement in reliability is disclosed. The nitride-based light emitting device includes a light emitting layer including a quantum well layer and a quantum barrier layer, and a stress accommodating layer arranged on at least one surface of the quantum well layer of the light emitting layer.

Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.

Abstract: Graphene layers, hexagonal boron nitride (hBN) layers, as well as other materials made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, the present invention provides graphene and hBN devices. In one aspect, for example, an electronic device is provided including a graphene layer and a planar hBN layer operably associated with the graphene layer and forming a functional interface therebetween. Numerous functional interfaces are contemplated, depending on the desired functionality of the device.

Abstract: Bistable carbazole compounds of formula (I) are described, wherein M is Fe, Co, Ru or Os, preferably Fe, useful as basic functional units for computing systems based on the QCA (Quantum Cellular Automata) paradigm; a process for their preparation is also described.

Abstract: A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

Abstract: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A composite structure includes; graphene and at least one substantially one-dimensional nanostructure disposed on the graphene.

Abstract: Provided are a semiconductor substrate including an uneven structure disposed on a surface of a substrate, a buffer layer disposed on the uneven structure, the buffer layer having an acicular structure, a compound semiconductor layer disposed on the buffer layer to planarize the uneven structure, and a plurality of voids defined between the substrate and the compound semiconductor layer, and a method for manufacturing the same. Thus, since the acicular structure disposed on the uneven structure of the substrate forms the voids on an interface between the substrate and the single crystal GaN layer to relax a stress due to a lattice mismatch and intercept propagation of a breakdown potential, a warpage characteristic of the grown single crystal GaN layer may be reduced, as well as, crystallinity may be improved.

Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.

Abstract: A nanodevice, a transistor including the nanodevice, a method of manufacturing the nanodevice, and a method of manufacturing the transistor including the nanodevice are provided. The nanodevice includes a substrate, a mask layer located on the substrate and having at least one opening, and a nanotube formed on the substrate through the opening along an edge of the opening. The nanotube extends through the opening in a direction substantially perpendicular to a surface of the substrate.

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.

Abstract: This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs.

Abstract: Various embodiments provide thin-walled structures and methodologies for their formation. In one embodiment, the thin-walled structure can be formed by disposing a semiconductor material in a patterned aperture using a selective growth mask that includes a plurality of patterned apertures, followed by a continuous growth of the semiconductor material using a pulsed growth mode. The patterned aperture can include at least one lateral dimension that is small enough to allow a threading defect termination at sidewall(s) of the formed thin-walled structure. In addition, high-quality III-N substrate structures and core-shell MQW active structures can be formed from the thin-walled structures for use in devices like light emitting diodes (LEDs), lasers, or high electron mobility transistors (HEMTs).

Abstract: Provided is a ZnO-based semiconductor device capable of achieving easier conversion into p-type by alleviating the self-compensation effect and by preventing donor impurities from mixing in. The ZnO-based semiconductor device includes a MgxZn1-xO substrate (0?x?1) having such a principal surface that: a projection axis obtained by projecting a normal line to the principal surface onto a plane formed by an a-axis and a c-axis of substrate crystal axes is inclined towards the a-axis by an angle of ?a degrees; a projection axis obtained by projecting the normal line to the principal surface onto a plane formed by an m-axis and the c-axis of the substrate crystal axes is inclined towards the m-axis by an angle of ?m degrees; the angle ?a satisfies 70?{90?(180/?)arctan(tan(??a/180)/tan(??m/180))?110; and the angle ?m?1.

Abstract: A semiconductor structure having an electrically conducting silicon substrate and a GaN semiconductor device separated from the substrate by a buffer layer is provided. The buffer layer electrically connects the silicon substrate with the GaN semiconductor device. In addition, a GaN LED arranged in a flip chip orientation on the buffer layer on the substrate is provided.

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

Abstract: A radiation-emitting semiconductor body includes a contact layer and an active zone. The semiconductor body has a tunnel junction arranged between the contact layer and the active zone. The active zone has a multi-quantum well structure containing at least two active layers that emit electromagnetic radiation when an operating current is impressed into the semiconductor body.

Abstract: A light emitting device can be used for light emitting diodes and laser diodes. The light emitting device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a multi-quantum well structure including at least one well layer and at least one barrier layer between the first and second semiconductor layers. A carrier trap portion is formed in at least one layer within the multi-quantum well structure. The at least one carrier trap portion is distributed at a higher density than a dislocation density of the layer including the carrier trap portion, and the carrier trap portion has a size of 1˜10 nm.

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.

Abstract: A nitride semiconductor device includes n-type and p-type nitride semiconductor layers, an active layer, the active layer having a lamination of quantum barrier layers and quantum well layers, a thermal stress control layer disposed between the n-type nitride semiconductor layer and the active layer, and formed of a material having a smaller thermal expansion coefficient than the n-type and p-type nitride semiconductor layers, and a lattice stress control layer disposed between the thermal stress control layer and the active layer, and including a first layer and a second layer.

Abstract: Disclosed is a nanostructure including a first set of nanowires formed from filling a plurality of voids of a template. The nanostructure also includes a second set of nanowires formed from filling a plurality of spaces created when the template is removed, such that the second set of nanowires encases the first set of nanowires. Several methods are also disclosed. In one embodiment, a method of fabricating a nanostructure including nanowires is disclosed. The method may include forming a first set of nanowires in a template, removing a first portion of the template, thereby creating spaces between the first set of nanowires, forming a second set of nanowires in the spaces between the first set of nanowires, and removing a second portion of the template.

Abstract: A method of fabricating a light emitting device includes modulating a crystal growth parameter to grow a quantum well layer that is inhomogeneous and that has a non-random composition fluctuation across the quantum well layer.

Abstract: An array of thyristor detector devices is provided having an epitaxial growth structure with complementary types of modulation doped quantum well interfaces located between a P+ layer and an N+ layer. The thyristor detector devices operate over successive cycles that each include a sequence of two distinct modes: a setup mode and a signal acquisition mode. During the setup mode, the n-type quantum well interface and/or the p-type quantum well interface is(are) substantially emptied of charge. During the signal acquisition mode, photocurrent is generated by the thyristor detector device in response to the absorption of incident electromagnetic radiation therein, which can induce the thyristor detector device to switch from an OFF state to an ON state. The OFF/ON state of the thyristor detector device produces an output digital electrical data that corresponds to the amount of incident radiation absorbed by the thyristor detector device during the signal acquisition mode of the current cycle.

Abstract: A nitride semiconductor device is provided. In the device, first and second conductivity type nitride layers are formed. An active layer is formed between the first and second conductivity type nitride layers. The active layer includes at least one quantum barrier layer and at least one quantum well layer. Also, a current spreading layer is interposed between the first conductivity type nitride layer and the active layer. The current spreading layer has an In content greater than the quantum well layer of the active layer.

Abstract: A superlattice structure comprises a plurality of well layers made of first semiconductor and a plurality of barrier layers made of second semiconductor that has a band gap wider than that of the first semiconductor, wherein both layers are deposited alternately, and wherein a maximum thickness of each of the wall and barrier layers is such that a band gap between a lower limit of a mini band generated in a conduction band and an upper limit of a mini band generated in a valence band is a given width in the energy state of electron of the superlattice structure, and a minimum thickness of each of the wall and the barrier layers is such that a bandwidth of a mini band generated in the conduction band is a given width in the energy state of electron of the superlattice structure.

Abstract: A CNT channel layer of a transistor is cut along a direction perpendicular to the channel to form a plurality of CNT patches, which are used to connect between a source and a drain. The arrangement of the CNT channel layer formed of a plurality of CNT patches can increase the probability that part of CNT patches becomes a semiconductive CNT patch. Since part of a plurality of CNT patches forming the channel layer is formed of a semiconductive CNT patch, a transistor having a good on/off ratio can be provided.

Abstract: A memory cell that includes a first magnetic layer, the magnetization of which is free to rotate under the influence of spin torque; a tunneling layer comprising a magnetic resonant tunneling diode (MRTD); and a second magnetic layer, wherein the magnetization of the second magnetic layer is pinned, wherein the tunneling layer is between the first magnetic layer and the second magnetic layer.

Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.

Abstract: Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm2/Vs.

Abstract: Hybrid crystalline organic-inorganic quantum confined systems are disclosed, which contain alternating layers of a bifunctional organic ligand and a II-VI semiconducting chalcogenide, wherein the semiconducting chalcogenide layers contain chalcogenides have the formula MQ, in which M is independently selected from II-VI semiconductor cationic species and Q is independently selected from S, Se and Te; and the bifunctional organic ligands of each organic ligand layer are bonded by a first functional group to an element M of an adjacent II-VI semiconducting chalcogenide layer and by a second functional group to an element M from the adjacent opposing II-VI semiconducting chalcogenide layer, so that the adjacent opposing II-VI semiconducting chalcogenide layers are linked by the bifunctional organic ligands of the organic ligand layers. Optical absorption experiments show that these systems produce a significant blue shift in their optical absorption edges, 1.2-1.5 eV, compared to a shift of 1.