Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.

Abstract: A semiconductor device includes a silicon substrate, an aluminum nitride layer which is arranged on the silicon substrate and has a region where silicon is doped thereof as an impurity, a buffer layer which is arranged on the aluminum nitride layer and has a structure where a plurality of nitride semiconductor films are laminated, and a semiconductor functional layer which is arranged on the buffer layer and made of nitride semiconductor.

Abstract: An exemplary nitride-based semiconductor device includes: a semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5° or the principal surface has a plurality of m-plane steps; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z>0) layer 26. The electrode 30 includes a Zn layer 32 and a Ag layer 34 provided on the Zn layer 32. The Zn layer is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal.

Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract: The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step (S110) serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step (S120) serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step (S120), the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 ?m and not more than 1 ?m on a line of 10 mm.

Abstract: A compound semiconductor device includes a substrate; and a compound semiconductor multilayer structure which is formed above the substrate and which contains compound semiconductors containing Group III elements, wherein the compound semiconductor multilayer structure has a thickness of 10 ?m or less and a percentage of aluminum atoms is 50% or more of the number of atoms of the Group III elements.

Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract: A method for manufacturing a semiconductor layer according to an embodiment of the present invention comprises preparing a first compound, preparing a second compound, making a semiconductor layer forming solution, and forming a semiconductor layer including a group compound by using this semiconductor layer forming solution. The first compound contains a first chalcogen-element-containing organic compound, a first Lewis base, a I-B group element, and a first III-B group element. The second compound contains an organic ligand and a second III-B group element. The semiconductor layer forming solution contains the first compound, the second compound, and an organic solvent.

Abstract: To provide a semiconductor diode with a part of a semiconductor lamination portion having a mesa structure portion, which is the part where a pn-junction is formed by lamination of an n-type semiconductor layer and a p-type semiconductor layer on a substrate, comprising: a protective insulating film formed by coating a main surface of the mesa structure portion, a side face of the mesa structure portion in which an interface of the pn-junction is exposed, and an etched and exposed surface of the n-type semiconductor layer; and an anode electrode formed in ohmic-contact with the p-type semiconductor layer exposed from an opening formed on a part of the main surface of the mesa structure portion of the protective insulating film, extending from the main surface, through the side face of the mesa structure portion, to the surface of the n-type semiconductor layer.

Abstract: A semiconductor device includes a main body made of a GaN-based semiconductor material, and at least one electrode structure. The electrode structure includes an ohmic contact layer that is formed on the main body, a buffer layer that is formed on the ohmic contact layer opposite to the main body, and a circuit layer that is made of a copper-based material and that is formed on the buffer layer opposite to the ohmic contact layer. The ohmic contact layer is made of a material selected from titanium, aluminum, nickel, and alloys thereof. The buffer layer is made of a material different from the material of the ohmic contact layer and selected from titanium, tungsten, titanium nitride, tungsten nitride, and combinations thereof.

Abstract: A GaN-based field effect transistor 101 comprises: a substrate 101; a channel layer 104 comprised of p-type GaN-based semiconductor material formed on the substrate 101; an electron supplying layer 106 formed on said channel layer 104 and comprised of GaN-based semiconductor material which has band gap energy greater than that of said channel layer 104; a gate insulating film 111 formed on a surface of said channel layer which was exposed after a part of said electron supplying layer was removed; a gate electrode 112 formed on said gate insulating film; a source electrode 109 and a drain electrode 110 formed so that said gate electrode 112 positions in between them; and a second insulating film 113 formed on said electron supplying layer, which is a different insulating film from said gate insulating film 111 and has electron collapse decreasing effect.

Abstract: A semiconductor device includes: a nitride semiconductor layer; a source electrode, a gate electrode and a drain electrode; an insulating layer covering at least the gate electrode and a part of the nitride semiconductor layer; and a field plate on the insulating layer, a width of a region of the field plate between an edge of the field plate of a side of the drain electrode and an edge of the side face of the insulating layer covering a side face of the gate electrode of a side of the drain electrode being 0.1 ?m or more, a distance between an edge of the field plate and an edge of the drain electrode in a contact face between the nitride semiconductor layer and the drain electrode being 3.5 ?m or more, an operating frequency of the semiconductor device being 4 GHz or less.

Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.

Abstract: The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method.

Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.

Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.

Abstract: Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [1-100], [-1010], and [01-01] of the substrate from a [0001] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.

Abstract: According to one embodiment, a nitride semiconductor device includes: a stacked foundation layer, and a functional layer. The stacked foundation layer is formed on an AlN buffer layer formed on a silicon substrate. The stacked foundation layer includes AlN foundation layers and GaN foundation layers being alternately stacked. The functional layer includes a low-concentration part, and a high-concentration part provided on the low-concentration part. A substrate-side GaN foundation layer closest to the silicon substrate among the plurality of GaN foundation layers includes first and second portions, and a third portion provided between the first and second portions. The third portion has a Si concentration not less than 5×1018 cm?3 and has a thickness smaller than a sum of those of the first and second portions.

Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.

Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.

Abstract: A power semiconductor module in which temperature rise of switching elements made of a Si semiconductor can be suppressed low and efficiency of cooling the module can be enhanced. To that end, the power semiconductor module includes switching elements made of the Si semiconductor and diodes made of a wide-bandgap semiconductor, the diodes are arranged in the middle region of the power semiconductor module, and the switching elements are arranged in both sides or in the periphery of the middle region of the power semiconductor module.

Abstract: A workpiece is implanted to improve growth of a compound semiconductor, such as GaN. This workpiece may be implanted such that the workpiece has a dose at a center different from a dose at a periphery. This workpiece also may be implanted one or more times to form a pattern of lines, which may be a grid, a series of circles, or other shapes. The distance between certain pairs of lines may be different across the workpiece.

Abstract: A group III nitride semiconductor free-standing substrate includes an as-grown surface, more than half of a region of the as-grown surface including a single crystal plane. The single crystal plane includes an off-angle inclined in an m-axis or a-axis direction from a C-plane with a group III polarity, or in a c-axis or a-axis direction from an M-plane.

Abstract: The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the 1-100 direction extends in a direction parallel to the striped openings of the growth mask.

Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.

Abstract: Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract: A bipolar power semiconductor device is provided with an emitter electrode on an emitter side and a collector electrode on a collector side. The device has a trench gate electrode and a structure with a plurality of layers of different conductivity types in the following order: at least one n doped source region, a p doped base layer, which surrounds the at least one source region, an n doped enhancement layer, a p doped additional well layer, an additional n doped enhancement layer, an additional p doped well layer, an n doped drift layer and a p doped collector layer. The trench gate electrode has a gate bottom, which is located closer to the collector side than the additional enhancement layer bottom.

Abstract: There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. In the present invention, the semiconductor device includes an n+-type GaN substrate 1 having a GaN layer that is in ohmic contact with a supporting substrate, a FET having an n?-type GaN drift layer 2 in a first region R1, and an SBD having an anode electrode in a second region R2, the anode electrode being in Schottky contact with the d?-type GaN drift layer 2. The FET and the SBD are arranged in parallel. A drain electrode D of the FET and a cathode electrode C of the SBD are formed on the back of the n+-type GaN substrate 1.

Abstract: Provided is a semiconductor device comprising a back barrier layer that is formed by a group III-V compound semiconductor above a substrate; a channel layer that is formed of a group III-V compound semiconductor having less bandgap energy than the back barrier layer, is formed on the back barrier layer, and includes a recessed portion formed in at least a portion of the channel layer above the back barrier layer to be thinner than other portions of the channel layer; a first electrode that is in ohmic contact with the channel layer; and a second electrode formed at least above the recessed portion of the channel layer.

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract: A method of fabricating a gallium nitride (GaN) thin layer structure includes forming a sacrificial layer on a substrate, forming a first buffer layer on the sacrificial layer, forming an electrode layer on the first buffer layer, forming a second buffer layer on the electrode layer, partially etching the sacrificial layer to form at least two support members configured to support the first buffer layer and define at least one air cavity between the substrate and the first buffer layer, and forming a GaN thin layer on the second buffer layer.

Abstract: Disclosed are a method for fabricating a quantum dot. The method includes the steps of (a) preparing a compound semiconductor layer including a quantum well structure formed by sequentially stacking a first barrier layer, a well layer and a second barrier layer; (b) forming a dielectric thin film pattern including a first dielectric thin film having a thermal expansion coefficient higher than a thermal expansion coefficient of the second barrier layer and a second dielectric thin film having a thermal expansion coefficient lower than the thermal expansion coefficient of the second barrier layer on the second barrier layer; and (c) heat-treating the compound semiconductor layer formed thereon with the dielectric thin film pattern to cause an intermixing between elements of the well layer and elements of the barrier layers at a region of the compound semiconductor layer under the second dielectric thin film.

Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.01<L<R<10 L (1) (in the expression (1), L represents the straight-line distance between the edge portions opposite to each other in a width direction of the trench).

Abstract: In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.

Abstract: Disclosed is a technique capable of preventing occurrence of warping in a nitride compound semiconductor layer, and by which a nitride compound semiconductor layer having small variations in the in-plane off angle can be grown with good reproducibility. Specifically disclosed is a method for producing a nitride compound semiconductor substrate using an HVPE process, wherein a low-temperature protective layer is formed on a rare earth perovskite substrate at a first growth temperature (a first step), and a thick layer composed of a nitride compound semiconductor is formed on the low-temperature protective layer at a second growth temperature that is higher than the first growth temperature (a second step). In the first step, the supply amounts of HCl and NH3 are controlled so that the supply ratio of HCl to NH3, namely the supply ratio III/V is 0.016-0.13, and the low-temperature protective layer has a film thickness of 50-90 nm.

Abstract: A power semiconductor module applied to a power converting apparatus for a railway car includes an element pair formed by connecting an IGBT and an SiC-FWD in anti-parallel to each other and an element pair formed by connecting an Si-IGBT and an SiC-FWD in anti-parallel to each other. The element pair and the element pair are housed in one module and configured as a 2-in-1 module in a manner that the first element pair operates as a positive side arm of the power converting apparatus and the second element pair operates as a negative side arm of the power converting apparatus. The element pairs are formed such that a ratio of an occupied area of SiC-FWD chips to an occupied area of IGBT chips in the element pairs is equal to or higher than 15% and lower than 45%.

Abstract: In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device.

Abstract: High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 106 cm?2.

Abstract: Disclosed is a semiconductor light emitting element (LC) provided with a substrate (110) having one surface on which plural hexagonal-pyramid-shaped protrusions (110b) are provided, a base layer (130) provided so as to be in contact with the surface on which the protrusions (110b) are provided, an n-type semiconductor layer (140) provided so as to be in contact with the base layer (130), a light emitting layer (150) provided so as to be in contact with the n-type semiconductor layer (140), and a p-type semiconductor layer (160) provided so as to be in contact with the light emitting layer (150). Each protrusion (110b) scatters light in lateral and oblique directions within the semiconductor light emitting element (LC). The protrusions are densely arranged on a substrate on which semiconductor layers are laminated, so that the light extraction efficiency is improved.

Abstract: A method according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor layer from a gas containing gallium, a gas containing nitrogen, and a gas containing indium. The concentration of indium in the III-nitride semiconductor structure is greater than zero and less than 1020 cm?3. A structure according to embodiments of the invention includes a super lattice of alternating first and second III-nitride layers. The first layers are more highly doped than the second layers. The average dopant concentration in the super lattice is less than 1020 cm?3.

Abstract: The nitride semiconductor light-emitting element of the invention has a stacked structure of a buffer layer, an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer, on one surface side of a single crystal substrate of a sapphire substrate. A nitride semiconductor multilayer structure as the buffer layer includes: a plurality of island-like nuclei formed of AlN and formed on the one surface of the single crystal substrate; a first nitride semiconductor layer formed of an AlN layer and formed on the one surface side of the single crystal substrate so as to fill gaps between adjacent nuclei and to cover all the nuclei; and a second nitride semiconductor layer formed of an AlN layer and formed on the first nitride semiconductor layer.

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract: The present invention provides a method for producing a trialkyl gallium comprising the steps of reacting gallium, magnesium, and an alkyl halide in an ether, and diluting during the reaction the reaction system with an ether; a method for producing a trialkyl gallium comprising the steps of heating in a vacuum a mixture of magnesium and molten gallium, and reacting the mixture with an alkyl halide in a solvent; and a method for producing a trialkyl gallium comprising the step of reacting an alkyl metal with an alkylgallium halide compound represented by the formula Ga2RmX6?m wherein R is a methyl or ethyl group, X is a halogen atom, and m is an integer from 1 to 5.

Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.

Abstract: A nitride semiconductor device having a high withstand voltage and being capable of reducing a leakage current, is provided. The nitride semiconductor device 30 of the present invention includes: a nitride semiconductor stack; an anode 36; and cathodes 37 and 38. The nitride semiconductor stack includes: a channel layer 33 and a wide bandgap layer 35, stacked in this order. The anode 36 forms a Schottky junction with the wide bandgap layer 35. The cathodes 37 and 38 are joined to the channel layer 33. The channel layer 33 is an n+-type nitride semiconductor layer. The bandgap of the wide bandgap layer 35 is wider than that of the channel layer 33.