Hetero-junction Transistor (epo) Patents (Class 257/E29.188)
  • Publication number: 20120132960
    Abstract: The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Inventor: Miguel E. Urteaga
  • Publication number: 20120126292
    Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erik M. Dahlstrom, Peter B. Gray, Qizhi Liu
  • Publication number: 20120098039
    Abstract: A SiGe HBT having low collector-base capacitance is disclosed, which includes: a silicon substrate, including isolation trenches, a collector region situated between the isolation trenches, and lateral trenches; a SiGe base layer formed on the silicon substrate; and an emitter region formed on the SiGe base layer. Each lateral trench is situated in the collector region on one side of an isolation trench, and is connected to the isolation trench. Moreover, a manufacturing method of a SiGe HBT having low collector-base capacitance is disclosed, which includes: performing ion implantation to predetermined regions in a silicon substrate before trench isolations are formed; forming lateral trenches by etching ion implantation regions after the trench isolations are formed; then forming a SiGe HBT device by an ordinary semiconductor process. The present invention can reduce the collector-base capacitance and therefore improve high-frequency characteristics of the device.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 26, 2012
    Inventors: Yan Miu, Changwa Yao, Hu Peng
  • Publication number: 20120091509
    Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 19, 2012
    Inventors: Donghua Liu, Wensheng Qian
  • Publication number: 20120074465
    Abstract: A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 29, 2012
    Inventors: Fan Chen, Xiongbin Chen, Wensheng Qian, Zhengliang Zhou
  • Publication number: 20120068228
    Abstract: A heterojunction bipolar transistor (HBT) structure with GaPSbAs base is disclosed. The HBT structure generally includes a substrate, a subcollector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and a contact layer laminated from bottom to top sequentially, and optionally may further comprise a buffer layer between the substrate and the subcollector layer. The subcollector layer includes heavily-doped GaAs; the collector layer includes GaAs, InGaP, or AlGaAs; the base layer includes GaPAsSb compound; the emitter layer includes InGaP or AlGaAs; the emitter cap layer includes GaAs; the contact layer includes InGaAs; and the substrate includes semi-insulating GaAs. Since the base having GaPSbAs compound has lower band gap energy, the turn-on voltage of the transistors can be reduced.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Inventors: Yu-Chung Chin, Tsung-Hsin Su
  • Publication number: 20120056247
    Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 8, 2012
    Inventors: Donghua Liu, Wensheng Qian
  • Patent number: 8129725
    Abstract: A semiconductor sensor determines physical and/or chemical properties of a medium, in particular a pH sensor. The semiconductor sensor has an electronic component with a sensitive surface, said component being constructed for its part on the basis of semiconductors with a large band gap (wide-gap semiconductor). The sensitive surface is provided at least in regions with a functional layer sequence which has an ion-sensitive surface. The functional layer sequence has at least one layer which is impermeable at least for the medium and/or the materials or ions to be determined.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: March 6, 2012
    Assignee: MicroGan GmbH
    Inventors: Mike Kunze, Ingo Daumiler
  • Publication number: 20120037914
    Abstract: A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 16, 2012
    Applicant: NXP B.V.
    Inventors: Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Blandine Duriez, Evelyne Marie Josephe Fabienne Gridelet
  • Publication number: 20120025169
    Abstract: Transistors and methods for forming transistors from groups of nanostructures are disclosed herein. The transistor may be formed from an array of nanostructures that are grown vertically on a substrate. The nanostructures may have lower, middle and upper segments that may be formed with different materials and/or doping to achieve desired effects. Collectively, the lower segments may form the source or drain, with the middle segments collectively forming the channel. Alternatively, the lower segments could collectively form the emitter or collector, with the middle segments collectively forming the base. Transistor electrodes may be planar metal structures that surround sidewalls of the nanostructures. The transistors may be Field Effect Transistors (FETs) or bipolar junction transistors (BJTs). Heterojunction bipolar junction transistors (HBTs) and high electron mobility transistors (HEMTs) are possible.
    Type: Application
    Filed: August 2, 2010
    Publication date: February 2, 2012
    Applicant: SUNDIODE INC.
    Inventors: Danny E. Mars, James C. Kim, Sungsoo Yi
  • Publication number: 20120025269
    Abstract: A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 2, 2012
    Applicant: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Ray Parkhurst, Tarak Railkar, William Snodgrass
  • Patent number: 8101491
    Abstract: According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 24, 2012
    Assignee: NXP B.V.
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Tony Vanhoucke, Hans Mertens
  • Publication number: 20110316047
    Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.
    Type: Application
    Filed: August 29, 2011
    Publication date: December 29, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuma Nanjo, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
  • Patent number: 8084786
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 27, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Publication number: 20110309372
    Abstract: A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: VELOX SEMICONDUCTOR CORPORATION
    Inventors: Xiaobin XIN, Milan POPHRISTIC, Michael SHUR
  • Publication number: 20110291159
    Abstract: This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation. The present invention provides metal electrode with stress release structures to reduce the strain and stresses in these devices.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventors: Ishiang Shih, Cindy Xing Qiu, Chunong Qiu, Yi-Chi Shih
  • Publication number: 20110241075
    Abstract: A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0?xc?1, 0?yc?1, 0<xc+yc?1). In the first nitride semiconductor, a length of an a-axis on a surface side is longer than a length of an a-axis on a substrate side.
    Type: Application
    Filed: October 16, 2009
    Publication date: October 6, 2011
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Kazuki Ota
  • Publication number: 20110220965
    Abstract: A method of manufacturing a compound semiconductor device, includes: forming a compound semiconductor lamination structure over a substrate; forming a metal film over the compound semiconductor lamination structure; forming a source electrode and a drain electrode over the metal film; forming one of a metal oxide film and a metal nitride film by one of oxidizing and nitriding a part of the metal film; and forming a gate electrode over the metal oxide film or the metal nitride film.
    Type: Application
    Filed: January 18, 2011
    Publication date: September 15, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Toshihiro Ohki
  • Publication number: 20110198671
    Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
    Type: Application
    Filed: August 5, 2009
    Publication date: August 18, 2011
    Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
    Inventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
  • Patent number: 7968865
    Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 28, 2011
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, William E. Hoke, Steven D. Bernstein, Ralph Korenstein
  • Publication number: 20110147799
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 23, 2011
    Applicant: MICROLINK DEVICES, INC.
    Inventors: Noren Pan, Andree WIBOWO
  • Patent number: 7960758
    Abstract: A bipolar transistor and a radio frequency amplifier circuit capable of preventing thermal runaway in the bipolar transistor without affecting the radio frequency amplifier circuit, which includes: a direct-current (DC) bias terminal to which a DC bias is supplied; a DC base electrode connected to the DC terminal; a radio frequency (RF) power terminal to which a radio frequency signal is supplied; an RF base electrode connected to the RF terminal; and a base layer connected to the DC base electrode and the RF base electrode.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: June 14, 2011
    Assignee: Panasonic Corporation
    Inventor: Masahiro Maeda
  • Publication number: 20110121364
    Abstract: According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter.
    Type: Application
    Filed: October 26, 2010
    Publication date: May 26, 2011
    Applicant: NXP B.V.
    Inventors: Johannes Josephus Theodorus Marinus DONKERS, Tony VANHOUCKE, Hans MERTENS
  • Publication number: 20110108886
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Application
    Filed: October 11, 2010
    Publication date: May 12, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Patent number: 7923754
    Abstract: A bipolar transistor (1) comprising a subcollector layer (3), a collector layer (4, 5), a base layer (6) and an emitter layer (7) which are successively built up and having: the subcollector layer (3) formed with a projection (3A) and recesses (3B), an upper part above the projection constituting an intrinsic transistor region (1A) of the bipolar transistor; insulator layer (10) buried between the recesses of the subcollector layer and the collector layer (4); a boundary interface between the subcollector layer and the collector layer held between the insulator layers; the base layer (6) made of a single crystal layer and provided with a base electrode (12) on a region becoming an extrinsic base layer (6B) of the base layer; and the subcollector layer provided with a collector electrode (11). The bipolar transistor has advantages of its emitter made finer in width, a reduced parasitic capacitance between its base and collector and improved high-frequency characteristics.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: April 12, 2011
    Assignee: Japan Science and Technology Agency
    Inventors: Yasuyuki Miyamoto, Tohru Yamamoto, Masashi Ishida
  • Publication number: 20110073911
    Abstract: A semiconductor device including: a substrate, which has a composition represented by the formula: Ala?Ga1-a?N, wherein a? satisfies 0<a??1; an active layer, which is formed on the substrate, and which has a composition represented by the formula: Alm?Ga1-m?N, wherein m? satisfies 0?m?<1; a buffer layer disposed between the active layer and the substrate; and a first main electrode and a second main electrode, which are formed on the active layer, and which are separated from each other, wherein the semiconductor device is operated by electric current flowing between the first main electrode and the second main electrode in the active layer, and wherein the buffer layer has a composition represented by the formula: AlbIn1-bN, wherein a composition ratio b satisfies 0<b<1, wherein the composition ratio b satisfies m?<b<a?.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 31, 2011
    Applicant: SANKEN ELECTRIC CO., LTD.
    Inventor: Ken SATO
  • Publication number: 20110073912
    Abstract: In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Toshiharu Marui, Hideyuki Okita
  • Publication number: 20110073910
    Abstract: The nitride semiconductor material according to the present invention includes a group III nitride semiconductor and a group IV nitride formed on the group III nitride semiconductor, where an interface between the group III nitride semiconductor and the group IV nitride has a regular atomic arrangement. Moreover, an arrangement of nitrogen atoms of the group IV nitride in the interface and an arrangement of group III atoms of the group III nitride semiconductor in the interface may be substantially identical.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: Panasonic Corporation
    Inventors: Toshiyuki Takizawa, Tetsuzo Ueda
  • Patent number: 7915640
    Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventor: Masaya Uemura
  • Publication number: 20110068371
    Abstract: Provided is an HEMT exhibiting a normally-off characteristic and low on-state resistance, which includes a first carrier transport layer; two separate second carrier transport layers formed of undoped GaN and provided on two separate regions of the first carrier transport layer; and carrier supply layers formed of AlGaN and respectively provided on the two separate second carrier transport layers. The second carrier transport layers and the carrier supply layers are respectively formed through crystal growth on the first carrier transport layer. The heterojunction interface between the second carrier transport layer and the carrier supply layer exhibits high flatness, and virtually no growth-associated impurities are incorporated in the vicinity of the heterojunction interface. Therefore, reduction in mobility of 2DEG is prevented, and on-state resistance is reduced.
    Type: Application
    Filed: September 20, 2010
    Publication date: March 24, 2011
    Applicant: Toyoda Gosei Co., Ltd.
    Inventor: Toru Oka
  • Publication number: 20110062495
    Abstract: The current invention provides the design of the field effect transistor with lateral channel suitable for high voltage switching. In such a transistor, the electrical charge stored in the high electric field region has to vary as the transistor switches from ON to OFF state and back. The invention provides the method of calculating the necessary recharging path parameters based on the material parameters of the FET and desired blocking voltage, ON state resistance and switching speed. The invention can be used in power electronics by providing circuits and parts, for example, for electrical power distribution between power plant customers, for automotive, craft and space applications and many other applications where high voltage in excess of 400-600 V is involved.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Inventor: Alexei Koudymov
  • Publication number: 20110057198
    Abstract: A delta (?)-doped (10-10)-plane GaN transistor is disclosed. Delta doping can achieve a transistor having at least 10 times higher current density than a conventional (10-10)-plane GaN transistor.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 10, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Tetsuya Fujiwara, Stacia Keller, Umesh K. Mishra
  • Publication number: 20110057232
    Abstract: Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.
    Type: Application
    Filed: May 9, 2008
    Publication date: March 10, 2011
    Inventors: Scott T. Sheppard, R. Peter Smith, Yifeng Wu, Sten Heikman, Matthew Jacob-Mitos
  • Publication number: 20110042683
    Abstract: Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 24, 2011
    Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Olga Kryliouk, Timothy J. Anderson
  • Publication number: 20110037101
    Abstract: A semiconductor device includes an undoped GaN layer (13), an undoped AlGaN layer (14), and a p-type GaN layer (15). In the p-type GaN layer (15), highly resistive regions (15a) are selectively formed. Resistance of the highly resistive regions (15a) can be increased by introducing a transition metal, for example, titanium.
    Type: Application
    Filed: March 27, 2009
    Publication date: February 17, 2011
    Inventors: Kazushi Nakazawa, Toshiyuki Takizawa, Tetsuzo Ueda, Daisuke Ueda
  • Publication number: 20110037100
    Abstract: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.
    Type: Application
    Filed: October 26, 2010
    Publication date: February 17, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masahiro HIKITA, Tetsuzo UEDA
  • Publication number: 20110031532
    Abstract: A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.
    Type: Application
    Filed: February 1, 2010
    Publication date: February 10, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Toshihide KIKKAWA, Kenji IMANISHI
  • Publication number: 20110031530
    Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 10, 2011
    Inventor: Klaus Schruefer
  • Publication number: 20110006346
    Abstract: The present invention provides a semiconductor device that has high electron mobility while reducing a gate leakage current, and superior uniformity and reproducibility of the threshold voltage, and is also applicable to the enhancement mode type.
    Type: Application
    Filed: March 12, 2009
    Publication date: January 13, 2011
    Inventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Publication number: 20100314664
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Application
    Filed: July 29, 2010
    Publication date: December 16, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Patent number: 7842537
    Abstract: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Brian S. Doyle
  • Publication number: 20100283084
    Abstract: The bipolar transistor includes a heterojunction intrinsic base layer epitaxially grown on a collector layer. The intrinsic base layer is disposed on the collector layer surrounded by an isolation layer, and an N-type impurity layer is formed in a surface portion of the collector layer. The impurity concentration of the N-type impurity layer is higher than the impurity concentration of the collector layer under the N-type impurity layer. Between the N-type impurity layer and the intrinsic base layer, an epitaxially grown layer is formed, where the epitaxially grown layer is lower in impurity concentration than the N-type impurity layer and the intrinsic base layer.
    Type: Application
    Filed: March 24, 2010
    Publication date: November 11, 2010
    Inventors: Teruhito Ohnishi, Ken Idota, Atsushi Nakamura
  • Publication number: 20100244099
    Abstract: A semiconductor device comprises: a heterojunction, comprises a first region comprising a first III-V semiconductor; a second region adjacent to the first region and comprising a second III-V semiconductor material, wherein the second III-V semiconductor material comprises a material of graded concentration over a width of the second region; and a third region adjacent to the second region and comprising a third III-V semiconductor material, wherein the graded concentration is selection to provide substantially no conduction band discontinuity at a junction of the second region and the third region, or to provide a type I semiconductor junction at the junction of the second region and the third region.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Applicant: AGILENT TECHNOLGIES, INC.
    Inventor: Bing-Ruey Wu
  • Publication number: 20100237388
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 23, 2010
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren PAN, Andree Wibowo
  • Publication number: 20100202483
    Abstract: A method for producing light emission from a semiconductor structure, including the following steps: providing a semiconductor structure that includes a first semiconductor junction between an emitter region of a first conductivity type and a base region of a second conductivity type opposite to that of the first conductivity type, and a second semiconductor junction between the base region and a drain region; providing, within the base region, a region exhibiting quantum size effects; providing an emitter electrode coupled with the emitter region; providing a base/drain electrode coupled with the base region and the drain region; and applying signals with respect to the emitter and base/drain electrodes to obtain light emission from the semiconductor structure.
    Type: Application
    Filed: January 7, 2010
    Publication date: August 12, 2010
    Inventors: Gabriel Walter, Milton Feng, Nick Holonyak, JR.
  • Patent number: 7759703
    Abstract: A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: July 20, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun Soo Nam, Myoung Sook Oh, Ho Young Kim, Young Jun Chong, Hyun Kyu Yu
  • Publication number: 20100171151
    Abstract: An HBT according to this invention includes: a sub-collector layer; a collector layer formed on the sub-collector layer and the base layer including a first collector layer, a second collector layer, a third collector layer, and a fourth collector layer. The first collector layer is formed on the sub-collector layer, and is made of semiconductor different from semiconductor of which the second to the fourth collector layers are made. The fourth collector layer is formed on the first collector layer, and has an impurity concentration lower than an impurity concentration of the second collector layer. The second collector layer is formed on the fourth collector layer, and has an impurity concentration lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer. The third collector layer is formed between the second collector layer and the base layer.
    Type: Application
    Filed: December 29, 2009
    Publication date: July 8, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Kenichi MIYAJIMA, Akiyoshi TAMURA, Keiichi MURAYAMA, Hirotaka MIYAMOTO
  • Publication number: 20100140587
    Abstract: A method for manufacturing high-injection heterojunction bipolar transistor capable of being used as a photonic device is disclosed. A sub-collector layer is formed on a substrate. A collector layer is then deposited on top of the sub-collector layer. After a base layer has been deposited on top of the collector layer, a quantum well layer is deposited on top of the base layer. An emitter is subsequently formed on top of the quantum well layer.
    Type: Application
    Filed: October 16, 2008
    Publication date: June 10, 2010
    Inventors: Daniel N. Carothers, Andrew T.S. Pomerene
  • Publication number: 20100133586
    Abstract: Provided are a heterojunction bipolar transistor and a method of forming the same.
    Type: Application
    Filed: May 8, 2009
    Publication date: June 3, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byoung-Gue MIN, Jong-Min Lee, Seong-II Kim, Kyung-Ho Lee, Hyung-Sup Yoon, Eun-Soo Nam
  • Patent number: RE42423
    Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: June 7, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Martin E. Kordesch, Howard D. Bartlow, Richard L. Woodin