With One-dimensional Charge Carrier Gas Channel (e.g., Quantum Wire Fet) (epo) Patents (Class 257/E29.245)
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Publication number: 20110204331Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.Type: ApplicationFiled: March 26, 2008Publication date: August 25, 2011Inventors: Lars Samuelson, Claes Thelander
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Publication number: 20110204332Abstract: A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.Type: ApplicationFiled: January 31, 2011Publication date: August 25, 2011Applicants: Samsung Electronics Co., Ltd.Inventors: Eun-hong Lee, Seung-hun Hong, Un-jeong Kim, Hyung-woo Lee, Sung Myung
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Patent number: 7999251Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.Type: GrantFiled: September 11, 2006Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Jack O. Chu, Guy M. Cohen, John A. Ott, Michael J. Rooks, Paul M. Solomon
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Publication number: 20110193053Abstract: A method of fabricating semiconductor nanowires (5) on a substrate (1) having a metallic oxide layer (2), includes: a) exposing the metallic oxide layer to a hydrogen plasma (11) of power P for a duration t suitable for reducing the layer and for forming metallic nanodrops (3) of radius (Rm) on the surface of the metallic oxide layer; b) low temperature plasma-assisted deposition of a thin layer (4) of a semiconductor material on the metallic oxide layer including the metallic nanodrops, the thin layer having a thickness (Ha) suitable for covering the metallic nanodrops; and c) thermal annealing at a temperature T sufficient to activate lateral growth of nanowires by catalysis of the material deposited as a thin layer from the metallic nanodrops. Also described are nanowires obtained by this method and nanometric transistors including a semiconductor nanowire, for forming a semiconductive connection between a source (16), a drain (17), and a gate (18).Type: ApplicationFiled: October 9, 2009Publication date: August 11, 2011Applicants: ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Pere Roca I Cabarrocas, Linwei Yu
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Publication number: 20110175063Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lidija Sekaric, Tymon Barwicz, Dureseti Chidambarrao
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Patent number: 7982204Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.Type: GrantFiled: May 27, 2010Date of Patent: July 19, 2011Assignee: Intel CorporationInventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
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Publication number: 20110168980Abstract: A nanofiber composite including a nanofiber formed of a hydrophobic polymer, a nanowire formed of a conductive or semiconductive organic material that is oriented in the nanofiber in the longitudinal direction of the nanofiber, and an ionic active material.Type: ApplicationFiled: June 30, 2010Publication date: July 14, 2011Inventors: Jae-hyun Hur, Jong-jin Park, Seung-nam Cha, Jong-min Kim, Chi-yul Yoon
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Publication number: 20110156004Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Inventors: Marko Radosavljevic, Uday Shah, Gilbert Dewey, Niloy Mukherjee, Robert S. Chau, Jack Kavalieros, Ravi Pillarisetty, Titash Rakshit, Matthew V. Metz
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Publication number: 20110147714Abstract: A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier.Type: ApplicationFiled: June 14, 2010Publication date: June 23, 2011Applicants: Samsung Electronics Co., Ltd., Seoul University Research and Business FoundationInventors: Seung Hun HONG, Byeong Ju KIM, Moon Sook LEE
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Publication number: 20110147709Abstract: A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: An Chen, Zoran Krivokapic
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Publication number: 20110147715Abstract: The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.Type: ApplicationFiled: June 16, 2009Publication date: June 23, 2011Applicant: PURDUE RESEARCH FOUNDATIONInventors: John A. Rogers, Qing Cao, Muhammad Alam, Ninad Pimparkar
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Publication number: 20110140086Abstract: The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centres (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centres (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centres (10) alters the conductivity of the nanowire (3).Type: ApplicationFiled: July 2, 2009Publication date: June 16, 2011Applicant: QuNano ABInventors: Lars Samuelson, Claes Thelander, Jonas Ohlsson, Anders Mikkelsen
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Patent number: 7960251Abstract: Disclosed herein is a method for producing nanowires. The method comprises the steps of providing a porous template with a plurality of holes in the form of tubes, filling the tubes with nanoparticles or nanoparticle precursors, and forming the filled nanoparticles or nanoparticle precursors into nanowires. According to the method, highly rectilinear and well-ordered nanowires can be produced in a simple manner.Type: GrantFiled: June 6, 2006Date of Patent: June 14, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung Lyong Choi, Jong Min Kim, Eun Kyung Lee
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Patent number: 7956348Abstract: A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current between the first conductive members and the second conductive members. Another insulating member hardly passing a tunnel current between the first conductive members and the third conductive members. An electric field generated by a potential applied to the third conductive members has an effect on the sub-band of the first conductive members.Type: GrantFiled: May 26, 2005Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventor: Yasunao Katayama
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Publication number: 20110108803Abstract: A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.Type: ApplicationFiled: January 5, 2011Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
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Publication number: 20110108804Abstract: Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Jeffrey W. Sleight
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Publication number: 20110101302Abstract: Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes.Type: ApplicationFiled: November 5, 2010Publication date: May 5, 2011Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Chongwu Zhou, Chuan Wang, Jialu Zhang, Koungmin Ryu, Alexander Badmaev, Lewis Gomez De Arco
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Publication number: 20110089995Abstract: Provided is a graphene device and a method of manufacturing the same. The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.Type: ApplicationFiled: August 25, 2010Publication date: April 21, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Jin seong Heo, Sun-ae Seo, Dong-chul Kim, Yun-sung Woo, Hyun-jong Chung
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Patent number: 7928017Abstract: A method of forming a nanowire and a semiconductor device comprising the nanowire are provided. The method of forming a nanowire includes forming a patterned SiyGe1-y layer (where, y is a real number that satisfies 0?y<1) on a base layer, and forming a first oxide layer and at least one nanowire within the first oxide layer by performing a first oxidation process on the patterned SiyGe1-y layer.Type: GrantFiled: March 17, 2008Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-youn Kim, Joong S. Jeong, Eun-ju Bae
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Patent number: 7923310Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.Type: GrantFiled: July 17, 2007Date of Patent: April 12, 2011Assignee: Sharp Laboratories of America, Inc.Inventors: Mark A. Crowder, Yutaka Takafuji
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Publication number: 20110079769Abstract: A MOS transistor having a gate length shorter than twice the de Broglie wavelength of the charge carriers in the channel material, wherein the cross-sectional area of the channel region is decreased in the vicinity of the drain region along at least one dimension to a value smaller than half said wavelength.Type: ApplicationFiled: March 7, 2006Publication date: April 7, 2011Inventor: Nicolas Cavassilas
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Publication number: 20110079770Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of exiting printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.Type: ApplicationFiled: September 14, 2010Publication date: April 7, 2011Applicant: William Marsh Rice UniversityInventors: Gyou-Jin Cho, Min Hun Jung, Jared L. Hudson, James M. Tour
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Publication number: 20110062418Abstract: A carbon nanotube electronic circuit utilizing a differential amplifier is implemented on a single carbon nanotube. Field effect transistors are formed from a first group of electrical conductors in contact with the carbon nanotube and a second group of electrical conductors insulated from, but exerting electric fields on, the carbon nanotube form the gates of the field effect transistors. A signal input circuit has a first input portion and a second input portion. A first field effect transistor electrically responsive to a first incoming signal is formed on the first input portion. A carbon nanotube actuator having electrical terminals and responsive to electrical conditions is an electrical load. A current source, connected to the signal input circuit, is formed on the carbon nanotube from one or more second field effect transistors.Type: ApplicationFiled: November 22, 2010Publication date: March 17, 2011Inventor: Lester F. Ludwig
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Publication number: 20110057168Abstract: A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size LS and the first electrode and the second electrode have an interval D therebetween, LS/D?10 is satisfied.Type: ApplicationFiled: August 26, 2010Publication date: March 10, 2011Applicant: SONY CORPORATIONInventor: Toshiyuki Kobayashi
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Publication number: 20110049476Abstract: An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material.Type: ApplicationFiled: August 30, 2010Publication date: March 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mikael T. Bjoerk, Oliver Hayden, Joachim Knoch, Emanuel Loertscher, Heike E. Riel, Walter Heinrich Riess, Heinz Schmid
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Patent number: 7880318Abstract: A sensing system includes a nanowire, a passivation layer established on at least a portion of the nanowire, and a barrier layer established on the passivation layer.Type: GrantFiled: April 27, 2007Date of Patent: February 1, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Theodore I. Kamins, Zhiyong Li, Duncan R. Stewart
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Publication number: 20110018065Abstract: A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20?) obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20?); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20? may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.Type: ApplicationFiled: February 17, 2009Publication date: January 27, 2011Applicant: NXP B.V.Inventors: Gilberto Curatola, Prabhat Agarwal, Mark J. H. Van Dal, Vijayaraghavan Madakasira
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Publication number: 20110012090Abstract: A silicon-germanium nanowire structure arranged on a support substrate is disclosed, The silicon-germanium nanowire structure includes at least one germanium-containing supporting portion arranged on the support substrate, at least one germanium-containing nanowire disposed above the support substrate and arranged adjacent the at least one germanium-containing supporting portion, wherein germanium concentration of the at least one germanium-containing nanowire is higher than the at least one germanium-containing supporting portion. A transistor comprising the silicon-germanium nanowire structure arranged on a support substrate is also provided. A method of forming a silicon-germanium nanowire structure arranged on a support substrate and a method of forming a transistor comprising forming the silicon-germanium nanowire structure arranged on a support substrate are also disclosed.Type: ApplicationFiled: December 7, 2007Publication date: January 20, 2011Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Navab Singh, Jiang Yu, Guo Qiang Patrick Lo
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Publication number: 20110012085Abstract: A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.Type: ApplicationFiled: September 24, 2007Publication date: January 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
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Publication number: 20110012177Abstract: A structure and a method for a semiconductor including a nanostructure semiconductor channel. The semiconductor may include a dielectric and an electrode, the electrode attached to the dielectric, a semiconductor channel may be disposed proximate to the dielectric, wherein the semiconductor channel has an electric mobility and is configured to have at least one dimension, and wherein the dielectric may be configured to apply a force at the at least one dimension.Type: ApplicationFiled: July 20, 2009Publication date: January 20, 2011Inventors: Dureseti Chidambarrao, Oki Gunawan, Xiao Hu Liu, Amlan Majumdar, Lidija Sekaric, Jeffrey W. Sleight
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Publication number: 20110001118Abstract: A method of patterning nanostructures comprising printing an ink comprising the nanostructures onto a solvent-extracting first surface such that a pattern of nanostructures is formed on the first surface.Type: ApplicationFiled: February 23, 2009Publication date: January 6, 2011Inventors: Kumar Bhupendra, Yuanyuan Zhang, Zongbin Wang, Lain-Jong Li, Subodh Gautam Mhaisalkar
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Publication number: 20100330687Abstract: Techniques for ultra-sensitive detection are provided. In one aspect, a detection device is provided. The detection device comprises a source; a drain; a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and a gate in close proximity to the nanowire.Type: ApplicationFiled: July 31, 2006Publication date: December 30, 2010Applicant: International Business Machines CorporationInventors: Ali Afzali - Ardakani, Sudhir Gowda, Supratik Guha, Hendrik F. Hamann, Emanuel Tutuc
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Publication number: 20100327259Abstract: Techniques for ultra-sensitive detection are provided. In one aspect, a detection device is provided. The detection device comprises a source; a drain; a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and a gate in close proximity to the nanowire.Type: ApplicationFiled: July 15, 2010Publication date: December 30, 2010Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Sudhir Gowda, Supratik Guha, Hendrik F. Hamann, Emanuel Tutuc
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Publication number: 20100327261Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: September 7, 2010Publication date: December 30, 2010Applicant: INTEL CORPORATIONInventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Peter G. Tolchinsky
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Publication number: 20100320438Abstract: Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates.Type: ApplicationFiled: May 14, 2010Publication date: December 23, 2010Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Cherie R. Kagan, Rudolf Tromp
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Publication number: 20100320437Abstract: The invention provides methods functionalizing a planar surface of a graphene layer, a graphite surface, or microelectronic structure. The graphene layer, graphite surface, or planar microelectronic structure surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the graphene layer, a graphite surface, or planar microelectronic surface while providing a functionalization layer of chemically functional groups, to produce a functionalized graphene layer, graphite surface, or planar microelectronic surface.Type: ApplicationFiled: June 10, 2008Publication date: December 23, 2010Applicant: President and Fellows of Harvard CollegeInventors: Roy G. Gordon, Damon B. Farmer
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Publication number: 20100314609Abstract: Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.Type: ApplicationFiled: November 19, 2009Publication date: December 16, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Han Young YU, Byung Hoon Kim, Soon Young Oh, Yong Ju Yun, Yark Yeon Kim, Won Gi Hong
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Publication number: 20100314604Abstract: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.Type: ApplicationFiled: August 19, 2010Publication date: December 16, 2010Inventors: Sung-Dae Suk, Dong-Won Kim, Kyoung-Hwan Yeo
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Publication number: 20100295024Abstract: A semiconductor structure includes a support and at least one block provided on the support. The block includes a stack including alternating layers based on a first semiconductor material and layers based on a second semiconductor material different from the first material, the layers presenting greater dimensions than layers such that the stack has a lateral tooth profile and a plurality of spacers filling the spaces formed by the tooth profile, the spacers being made of a third material different from the first material such that each of the lateral faces of the block presents alternating lateral bands based on the first material and alternating lateral bands based on the third material. At least one of the lateral faces of the block is partially coated with a material promoting the growth of nanotubes or nanowires, the catalyst material exclusively coating the lateral bands based on the first material or exclusively coating the lateral bands based on the third material.Type: ApplicationFiled: May 18, 2010Publication date: November 25, 2010Applicant: Commissariat a 1'Energie Atomique et aux Energies AlternativesInventors: Carole Pernel, CÉCILIA DUPRE
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Publication number: 20100295023Abstract: Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting material. In one embodiment, the FETs are vertical arrangements of SWCNTs, and in some embodiments prepared within porous anodic alumina (PAA). Various embodiments pertain to different methods for fabricating the drains, sources, and gates.Type: ApplicationFiled: April 6, 2010Publication date: November 25, 2010Applicant: PURDUE RESEARCH FOUNDATIONInventors: Aaron D. Franklin, Timothy D. Sands, Timothy S. Fisher, David B. Janes
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Publication number: 20100283031Abstract: A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost.Type: ApplicationFiled: September 29, 2008Publication date: November 11, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Tae Youb KIM, Chil Seong Ah, Chang Geun Ahn, Han Young Yu, Jong Heon Yang, Moon Gyu Jang
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Patent number: 7829880Abstract: A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number of the quantum dots and the magnitude of strain of the side barrier layer from which each of the quantum dot layers is formed are set so that a gain spectrum of the active layer has a flat gain bandwidth corresponding to a shift amount of the gain spectrum within a desired operation temperature range.Type: GrantFiled: March 13, 2008Date of Patent: November 9, 2010Assignees: Fujitsu Limited, The University of TokyoInventors: Hiroji Ebe, Kenichi Kawaguchi, Ken Morito, Yasuhiko Arakawa
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Publication number: 20100279426Abstract: Electronic devices comprising a dielectric material, at least one carbon sheet, and two electrode terminals are described herein. The devices exhibit non-linear current-versus-voltage response over a voltage sweep range in various embodiments. Uses of the electronic devices as two-terminal memory devices, logic units, and sensors are disclosed. Processes for making the electronic devices are disclosed. Methods for using the electronic devices in analytical methods are disclosed.Type: ApplicationFiled: September 29, 2008Publication date: November 4, 2010Applicant: William Marsh Rice UniversityInventors: James M. Tour, Yubao Li, Alexander Sinitskiy
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Publication number: 20100276662Abstract: A junctionless metal-oxide-semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second, and third portions. The second portion is located between the first and third portions. The first, second, and third portions are doped with dopants of the same polarity and the same concentration. The transistor device further comprises an electrode connected to the second portion. A current flows between the first and third portions when a voltage is applied to the electrode.Type: ApplicationFiled: April 2, 2010Publication date: November 4, 2010Applicant: University College Cork, National University of IrelandInventor: Jean-Pierre Colinge
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Publication number: 20100270536Abstract: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.Type: ApplicationFiled: July 6, 2010Publication date: October 28, 2010Applicant: ETAMOTA CORPORATIONInventor: Thomas W. Tombler, JR.
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Publication number: 20100270530Abstract: A method for manufacturing a biosensor device is provided. The method involves forming a silicon nanowire channel with a line width of several nanometers to several tens of nanometers using a typical photolithography process, and using the channel to manufacture a semiconductor nanowire sensor device.Type: ApplicationFiled: July 24, 2008Publication date: October 28, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Chan Woo Park, Chang Geun Ahn, Jong Heon Yang, In Book Baek, Chil Seong Ah, Han Young Yu, An Soon Kim, Tae Youb Kim, Moon Gyu Jang, Myung Sim Jun
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Publication number: 20100264403Abstract: A method for forming an electronic switching device on a substrate, wherein the method comprises depositing the active semiconducting layer of the electronic switching device onto the substrate from a liquid dispersion of ligand-modified colloidal nanorods, and subsequently immersing the substrate into a growth solution to increase the diameter and/or length of the nanorods on the substrate, and wherein the as-deposited nanorods are aligned such that their long-axis is aligned preferentially in the plane of current flow in the electronic switching device.Type: ApplicationFiled: August 9, 2006Publication date: October 21, 2010Inventors: Henning Sirringhaus, Baoquan Sun
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Publication number: 20100252813Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.Type: ApplicationFiled: July 17, 2007Publication date: October 7, 2010Applicant: SHARP LABORATORIES OF AMERICA, INC.Inventors: Mark A. Crowder, Yutaka Takafuji
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Publication number: 20100252434Abstract: Embodiments of the present invention provide a method and apparatus for selective electrokinetic separation. In an embodiment, a local gate electric field is applied to a voltage-gated nanochannel filled with an aqueous solution. Additionally, a surface charge may be present on the walls of the nanochannel. This local gate electric field shows a selective quenching feature of ionic density and behaves as a potential shield against selective charge from entering the nanochannel while facilitating transport of the opposite charge. Embodiments of the subject method can also be used to enhance osmotic diffusion of selective electrolytes through biological cells. Specific embodiments can be useful as a biosensor since most biological cells contain an aqueous solution. A surface charge and local gate electric field can be applied to a biological cell to selectively separate molecules, such as proteins or ions.Type: ApplicationFiled: August 28, 2008Publication date: October 7, 2010Applicant: University of Florida Research Foundation, Inc.Inventor: Subrata Roy
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Patent number: 7808056Abstract: A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer.Type: GrantFiled: October 11, 2007Date of Patent: October 5, 2010Assignee: NEC Electronics CorporationInventors: Hiroshi Furuta, Junji Monden, Shouzou Uchida, Muneaki Matsushige