With One-dimensional Charge Carrier Gas Channel (e.g., Quantum Wire Fet) (epo) Patents (Class 257/E29.245)
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Publication number: 20100207103Abstract: A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture.Type: ApplicationFiled: May 3, 2010Publication date: August 19, 2010Applicant: NEW JERSEY INSTITUTE OF TECHNOLOGYInventors: Reginald Conway Farrow, Amit Goyal
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Publication number: 20100200834Abstract: Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.Type: ApplicationFiled: March 22, 2010Publication date: August 12, 2010Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
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Publication number: 20100187503Abstract: A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si1-xGex layer (0<x<0.5) on the (100) plane of the Ge nano wire.Type: ApplicationFiled: January 27, 2010Publication date: July 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko MORIYAMA, Yoshiki Kamata, Tsutomu Tezuka
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Patent number: 7763978Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.Type: GrantFiled: March 28, 2007Date of Patent: July 27, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Wei Wu, R. Stanley Williams, Warren Robinett, Gregory S. Snider, Zhaoning Yu, Shih-Yuan Wang, Duncan Stewart
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Patent number: 7737429Abstract: Disclosed are a nitride based semiconductor device, including a high-quality GaN layer formed on a silicon substrate, and a process for preparing the same. A nitride based semiconductor device in accordance with the present invention comprises a plurality of nanorods aligned and formed on the silicone substrate in the vertical direction; an amorphous matrix layer filling spaces between nanorods so as to protrude some upper portion of the nanorods; and a GaN layer formed on the matrix layer.Type: GrantFiled: August 16, 2005Date of Patent: June 15, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Min Ho Kim, Masayoshi Koike, Kyeong Ik Min, Seong Suk Lee, Sung Hwan Jang
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Publication number: 20100133509Abstract: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.Type: ApplicationFiled: June 4, 2008Publication date: June 3, 2010Applicant: PANASONIC CORPORATIONInventors: Takahiro Kawashima, Tohru Saitoh
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Publication number: 20100090293Abstract: Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom.Type: ApplicationFiled: October 1, 2009Publication date: April 15, 2010Applicant: PEKING UNIVERSITYInventors: Zhiyong ZHANG, Lianmao PENG, Sheng WANG, Xuelei LIANG, Qing CHEN
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Publication number: 20100072460Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.Type: ApplicationFiled: September 22, 2009Publication date: March 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mikael T. Bjoerk, Joachim Knoch, Heike E. Riel, Walter Heinrich Riess, Heinz Schmid
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Patent number: 7638397Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.Type: GrantFiled: August 25, 2008Date of Patent: December 29, 2009Assignee: Intel CorporationInventor: Brian Doyle
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Publication number: 20090302306Abstract: Disclosed herein are a nano electronic device and a method of fabricating the same. The nano electronic device includes a ferroelectric nano-structure and a semiconducting nano-wire. Polarization formed on the ferroelectric nano-structure is utilized.Type: ApplicationFiled: April 5, 2006Publication date: December 10, 2009Inventors: Wan-Soo Yun, Sung-Oong Kang, Hyung-Ju Park
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Patent number: 7598516Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.Type: GrantFiled: January 7, 2005Date of Patent: October 6, 2009Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christophe G. M. M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
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Patent number: 7569941Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).Type: GrantFiled: December 22, 2006Date of Patent: August 4, 2009Assignee: The Regents of the University of CaliforniaInventors: Arun Majumdar, Ali Shakouri, Timothy D. Sands, Peidong Yang, Samuel S. Mao, Richard E. Russo, Henning Feick, Eicke R. Weber, Hannes Kind, Michael Huang, Haoquan Yan, Yiying Wu, Rong Fan
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Publication number: 20090114903Abstract: An integrated, multilayer nanotube and complementary metal oxide semiconductor (CMOS) device is provided along with a method of forming the same. The device includes at least one CMOS device formed on at least one layer of the device, a first metal wiring layer that is electrically connected to the least one CMOS device, and at least one nanotube device formed over the first metal wiring layer in parasitic isolation from the at least one CMOS device. In one or more embodiments, the at least one CMOS device and the at least one nanotube device are located on different layers of a same semiconductor wafer chip to allow the wafer to be is used for system-on-chip (SoC) applications having RF/analog circuitry based on the least one nanotube device and digital circuitry based on the at least one CMOS device.Type: ApplicationFiled: May 22, 2008Publication date: May 7, 2009Inventor: Amol M. Kalburge
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Patent number: 7521268Abstract: Provided is a method of manufacturing a display which includes an insulating substrate and a structure formed on the insulating substrate and including a display element, including forming a patterned layer as a portion of the structure on the insulating substrate by vapor deposition in vacuum using a mask, and cooling the insulating substrate before and/or during formation of the patterned layer by arranging a cooling plate which comprises a metal substrate and an infrared absorption layer covering a main surface of the metal substrate and being larger in infrared absorptance than the metal plate such that the infrared absorption layer faces the insulating substrate.Type: GrantFiled: August 23, 2005Date of Patent: April 21, 2009Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Motonobu Aoki, Tetsuo Ishida
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Publication number: 20080191196Abstract: The present invention generally relates to nanoscale heterostructures and, in some cases, to nanowire heterostructures exhibiting ballistic transport, and/or to metal-semiconductor junctions that that exhibit no or reduced Schottky barriers. One aspect of the invention provides a solid nanowire having a core and a shell, both of which are essentially undoped. For example, in one embodiment, the core may consist essentially of undoped germanium and the shell may consist essentially of undoped silicon. Carriers are injected into the nanowire, which can be ballistically transported through the nanowire. In other embodiments, however, the invention is not limited to solid nanowires, and other configurations, involving other nanoscale wires, are also contemplated within the scope of the present invention. Yet another aspect of the invention provides a junction between a metal and a nanoscale wire that exhibit no or reduced Schottky barriers.Type: ApplicationFiled: May 25, 2007Publication date: August 14, 2008Inventors: Wei Lu, Jie Xiang, Yue Wu, Brian P. Timko, Hao Yan, Charles M. Lieber
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Patent number: 7394118Abstract: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized.Type: GrantFiled: March 9, 2005Date of Patent: July 1, 2008Assignee: University of Southern CaliforniaInventor: Chongwu Zhou
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Publication number: 20080067495Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.Type: ApplicationFiled: June 20, 2007Publication date: March 20, 2008Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventor: Anne S. Verhulst
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Publication number: 20070262397Abstract: A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.Type: ApplicationFiled: July 12, 2005Publication date: November 15, 2007Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Radu Surdeanu, Prabhat Agarwal, Abraham Balkenende, Erik Bakkers
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Patent number: 7183597Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.Type: GrantFiled: December 13, 2004Date of Patent: February 27, 2007Assignee: Intel CorporationInventor: Brian Doyle