Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A method of manufacturing a semiconductor device, including forming a gate electrode or dummy gate on a fin-type silicon layer, introducing an impurity into the fin-type silicon layer with the gate electrode or dummy gate used as mask so as to form first impurity regions, etching the gate electrode or dummy gate so as to form a gate electrode or dummy gate having a reduced size, and introducing an impurity into the fin-type silicon layer with the gate electrode or dummy gate of the reduced size used as a mask so as to form second impurity regions positioned adjacent to the first impurity diffusion regions.

Abstract: To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7A, 7B are not directly contacted to the silicon nitride film 19.

Abstract: A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

Abstract: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered with the SiN film (21).

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

Abstract: A method of manufacturing a semiconductor device includes performing a first etching process on a gate electrode layer to form a gate electrode of a first transistor group including a transistor pair, and performing a second etching process different from the first etching on the gate electrode layer to form a gate electrode of a second transistor group. Forming in this way enables characteristics of the transistor pair to be the same.

Abstract: An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region I s formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity-drift portions of the HV-second-conductivity FET.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.