Abstract: A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of th

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

Abstract: The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit.

Abstract: A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate electrode of the first FET and a second gate electrode of the second FET are formed on the dielectric film, and a drain electrode and a source electrode are formed on the semiconductor film. Under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween, and the ends of the semiconductor film that forms the channel are located inwardly of the ends of the back-gate electrode.

Abstract: Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode.

Abstract: Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat mask to define a moat region, an NDT mask to define an N drift region, a PDT mask to define a P drift region, and a gate mask to form a gate. According to embodiments, a PDT mask may be configured to expose a field region of a semiconductor device.

Abstract: In one aspect of the present invention, a semiconductor device may include a plurality of fins disposed substantially parallel to each other at predetermined intervals on a semiconductor substrate, a gate electrode formed to partially sandwich therein the both side surfaces, in the longitudinal direction, of each of the plurality of fins with an insulating film interposed between the gate electrode and each of the side surfaces of each fin, and a semiconductor layer formed on each of at least some of side surfaces of the plurality of fins, wherein the semiconductor layer in a region located on an outer side surface, in the longitudinal direction, of each of two fins which are located at both ends of the line of the plurality of fins is thinner than the semiconductor layer in a region located on each of side surfaces, in the longitudinal direction and other than the outer surfaces of the two fins, of the plurality of fins.

Abstract: A semiconductor device 100 includes a first gate 210, which is formed using a gate last process. The first gate 210 includes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate electrode formed over the gate insulating film in the first concave portion; and a protective insulating film 140 formed on the gate electrode in the first concave portion. In addition, the semiconductor device 100 includes a contact 134, which is coupled to the N-type impurity-diffused region 116a in the both sides of the first gate 210 and is buried in the second concave portion having a diameter that is large than the first concave portion.

Abstract: A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a second surface opposite to the first surface; and incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface.

Abstract: A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer.

Abstract: A semiconductor device according to one embodiment includes: a substrate; a plurality of fins made of a semiconductor and formed on the substrate; a plurality of via contact regions formed between the fins, the plurality of via contact regions and the plurality of the fins constituting a closed loop structure; a gate contact region on the substrate arranged at a position surrounded by the closed loop structure; a plurality of gate electrodes connected to the gate contact region respectively, each of the plurality of gate electrodes sandwiching both side faces of each of the plurality of fins between its opposite regions via gate insulating film; and source/drain regions formed in regions in the plurality of fins and in the contact region, the regions being formed on both sides of a region sandwiched by the gate electrodes along longitudinal direction of the fin.

Abstract: Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.

Abstract: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

Abstract: Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Abstract: Double gate transistor microelectronic device comprising: a support, a structure suited to forming at least one multi-branch channel and comprising a plurality of separate parallel semi-conductor rods and situated in a plane orthogonal to the principal plane of the support, the rods linking a first block suited to forming a source region of the transistor and a second block provided, suited to forming a drain region of the transistor, a first gate electrode situated on one side of said structure against the sides of said semi-conductor rods, a second gate electrode, separate from the first gate and situated on another side of the structure against the opposite sides of the rods, the semi-conductor rods and one or several insulating rods situated between the semi-conductor rods, separating the first gate electrode and the second gate electrode.

Abstract: This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns (108a,128a,208a,228a,308a,328a) with a critical dimension less than the critical dimension of the transistor channel zone (104b). This method particularly includes a step to reduce double gate patterns, using isotropic etching. The invention also relates to a microelectronic device obtained using such a method.

Abstract: Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer.

Abstract: The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in the respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

Abstract: A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a gate insulating layer on a semiconductor substrate, a gate electrode on the gate insulating layer and source/drain regions in the semiconductor substrate at sides of the gate electrode. The gate electrode includes a first gate electrode and a second gate electrode on and electrically connected to the first gate electrode.

Abstract: In one embodiment of the present invention, trench sections cause regions where source diffusion sections and body diffusion sections are formed to be partitioned into line regions. The trench sections are formed not in a straight line shape but in a zigzag shape. Two adjacent trench sections are provided to be axisymmetric, having an axis of symmetry in a longitudinal direction of the trench sections. A wide region and a narrow region are alternately formed in each of the regions, partitioned by the trench sections, in which regions the source diffusion sections and the body diffusion sections are formed. Each of the body diffusion sections is formed in the wide region. This makes it possible to realize an improved power MOSFET that achieves a reduction in an ON resistance per unit cell and an increase in a layout effect.

Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.

Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

Abstract: Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin.

Abstract: A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.

Abstract: Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract: The semiconductor device according to the present invention is a Fin-FET that can substantially increase the channel width without unnecessarily elevating the height of the Fin. The Fin-FET has gate electrodes 22 formed on the upper surface, both left and right sides and the bottom surface of channel-forming semiconductor layer 11a formed by processing semiconductor substrate 11 into a fin shape; and a channel region the four surfaces of which are surrounded by gate electrodes 22.

Abstract: The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarized, where the channel has a multi-layer structure with at least three layers, and with at least one of the layers of the multi-layer structure having electrical properties that are substantially different from those of another layer of the multi-layer structure, and wherein a single gate or two gates are arranged substantially perpendicular to a reference plane of the channel defined by an interface plane between two layers of the multi-layer structure.

Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

Abstract: A semiconductor device includes a semiconductor layer disposed between a semiconductor substrate and a gate electrode, a back gate insulating layer pattern disposed between the semiconductor layer and the semiconductor substrate, and a gate insulating layer disposed between the semiconductor layer and the gate electrode. The semiconductor substrate extends from both sides of the back gate insulating layer pattern to the gate insulating layer and is directly in contact with a sidewall of the semiconductor layer.

Abstract: In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.

Abstract: A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin.

Abstract: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

Abstract: In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a load, a second terminal of the load coupled to a further reference source, the further MuGFET device configured to receive a further input signal at a gate thereof, and wherein the MuGFET device and the further MuGFET device are disposed above a substrate and configured to provide an output signal at the first terminal of the load.

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract: A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved.

Abstract: A semiconductor device includes a semiconductor substrate; a source area, a channel area and a drain area vertically stacked on the semiconductor substrate; and a gate formed in both side walls of the stacked source area, channel area and drain area under interposition of a gate insulation layer.

Abstract: In one aspect of the present invention, a semiconductor device may include a plurality of fins disposed substantially parallel to each other at predetermined intervals on a semiconductor substrate, a gate electrode formed to partially sandwich therein the both side surfaces, in the longitudinal direction, of each of the plurality of fins with an insulating film interposed between the gate electrode and each of the side surfaces of each fin, and a semiconductor layer formed on each of at least some of side surfaces of the plurality of fins, wherein the semiconductor layer in a region located on an outer side surface, in the longitudinal direction, of each of two fins which are located at both ends of the line of the plurality of fins is thinner than the semiconductor layer in a region located on each of side surfaces, in the longitudinal direction and other than the outer surfaces of the two fins, of the plurality of fins.

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract: A semiconductor structure includes an inverted T shaped gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate. The inverted T shaped gate electrode may comprise different gate electrode materials in a horizontal portion thereof and a vertical portion thereof. The semiconductor structure may be passivated with an inter-level dielectric (ILD) layer through which may be located and formed a plurality of vias that contact the plurality of source and drain regions. Due to the inverted T shaped gate electrode, the semiconductor structure exhibits a reduced gate electrode to via capacitance.

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes a semiconductor pillar, a gate insulating layer formed on a portion of a surface of the semiconductor pillar, a gate electrode formed on the gate insulating layer, and source/drain regions formed on portions of the semiconductor pillar where the gate electrode is not formed, in which the gate electrode includes a first gate electrode, a second gate electrode, and an inter-gate insulating layer, in which the first gate electrode has a work function higher than that of the second gate electrode, in which the inter-gate insulating layer is formed between the first gate electrode and the second gate electrode, and in which the first gate electrode and the second gate electrode are electrically connected by a contact or a metal interconnection line. A portion of the second gate electrode having the work function lower than that of the first gate electrode is overlapped by the drain region.

Abstract: A transistor, comprising a first gate structure formed on a substrate, and having a stacked structure of a first gate electrode and a first gate hard mask, a first gate spacer formed on sidewalls of the first gate structure, a second gate structure having a stacked structure of a second gate electrode and a second gate hard mask, the second gate structure surrounding both sidewalls and top surfaces of the first gate structure and the first gate spacer, and a second gate spacer formed on sidewalls of the second gate structure.