Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.

Abstract: In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Abstract: There are provided a CMOS image sensor and a method for fabrication thereof. The CMOS image sensor having a reset transistor, a select transistor, a drive transistor and a photodiode, includes an active region in shape of a line, a gate electrode of the drive transistor, which is intersected with the active region, a blocking layer interposed between the active region and the gate electrode in which the blocking layer is formed on an intersection region of the active region and the gate electrode, and a metal contact electrically connected to the gate electrode, wherein the metal contact is not electrically connected to the active region by the blocking layer.

Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material.

Abstract: A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.

Abstract: Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film.

Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

Abstract: The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.

Abstract: A semiconductor memory device has a substrate having a semiconductor layer, an n-type semiconductor region formed beneath a main surface of the semiconductor layer, a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the semiconductor layer, a charge storage layer formed on the gate insulating film, a charge block layer formed on the charge storage layer and a control gate electrode formed on the charge block layer, an insulating film between cells formed on the main surface of the semiconductor layer between the cell gates, and a carbon accumulation region formed in the insulating film between the cells and has a maximum concentration of a carbon element in a region within 2 nm from an interface between the semiconductor layer and the insulating film between the cells.

Abstract: Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

Abstract: A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.

Abstract: A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

Abstract: Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate; a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of the substrate to a first height of the fence-shaped body; a gate insulating layer formed at side walls and an upper surface of the fence-shaped body at which the insulating layer is not formed; a gate electrode formed on the gate insulating layer; source/drain formed at regions of the fence-shaped body where the gate electrode is not formed. The gate electrode includes first and second gate electrodes which are in contact with each other and have different work functions. Particularly, the second gate electrode having a low work function is disposed to be close to the drain.

Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

Abstract: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

Abstract: A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.

Abstract: A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

Abstract: In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with the fins in the first direction above the substrate. The gate line extends in a second direction above the substrate, and partially wraps around the fins. The gate contact landing pad is positioned adjacent to or above the dummy fin and electrically coupled to the gate line. The gate contact element is electrically coupled to the gate contact landing pad and is positioned to the top surface thereof.

Abstract: An electronic structure modulation transistor having two gates separated from a channel by corresponding dielectric layers, wherein the channel is formed of a material having an electronic structure that is modified by an electric field across the channel.

Abstract: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Abstract: A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.

Abstract: A semiconductor device. The device including: a planar FET formed in a single crystal-silicon substrate, the FET comprising a first channel region, first and second source drains on opposite sides of the first channel region and a gate, the gate over the channel region and electrically isolated from the channel region by a first gate dielectric layer; and a FinFET formed in single crystal silicon block on top of and electrically isolated from the substrate, the FinFET comprising a second channel region, third and fourth source drains on opposite first and second ends of a second channel region and the gate, the gate electrically isolated from the second channel region by a second gate dielectric layer.

Abstract: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

Abstract: The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract: A semiconductor switching element, wherein on a semiconductor layer formed on a substrate, or on a semiconductor substrate, a source electrode and a drain electrode are disposed at a predetermined interval in a direction along a surface of the substrate; and a second gate electrode is provided between the source electrode and the drain electrode, the second gate electrode is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.

Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Abstract: A full periphery multi-gate transistor with ohmic strip is disclosed. The multi-gate transistor comprises a substrate, a multi-layer structure, a source finger, a drain finger, and a gate. The gate is formed between the source finger and the drain finger, and then a conduction channel is formed between the source finger and the drain finger. The gate also meanderingly wraps around an end of the source finger and an end of the drain finger. Therefore, the end of the source finger and the end of the drain finger are parts of the conduction channel and both provide channel conductance. In addition, an ohmic strip is formed between two gate lines of the gate.

Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.

Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.

Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

Abstract: Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode connected to the active region pattern and disposed to be symmetric with respect to a line connecting the first and second gate electrodes, wherein the first and second gate electrodes and the source and drain electrodes are disposed on the same plane of the substrate.

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract: Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.

Abstract: A semiconductor device includes a first gate trench, a second gate trench, and a dummy gate trench provided in an active region extending in an X direction; and a first gate electrode, a second gate electrode, and a dummy gate electrode extending in a Y direction crossing the active region, at least a part of which are buried in the first gate trench, the second gate trench, and the dummy gate trench, respectively. The dummy gate electrode arranged between second and third diffusion layers isolates and separates a transistor constituted by the first gate electrode and first and second diffusion layers provided on both sides of the first gate electrode, respectively, from a transistor constituted by the second gate electrode and third and fourth diffusion layers provided on both sides of the second gate electrode, respectively.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.

Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.

Abstract: A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.

Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.

Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.