Monocrystalline Only (epo) Patents (Class 257/E29.286)
  • Patent number: 8742476
    Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: June 3, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist
  • Patent number: 8624400
    Abstract: A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata
  • Patent number: 8569803
    Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
  • Patent number: 8541843
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: September 24, 2013
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Rinn Cleavelin, Thomas Rueckes
  • Publication number: 20130193513
    Abstract: A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andres Bryant, Josephine B. Chang, Wilfried Haensch, Effendi Leobandung, Chung-Hsun Lin
  • Patent number: 8492843
    Abstract: A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Alvin J. Joseph, Robert M. Rassel, Yun Shi
  • Patent number: 8482069
    Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
  • Patent number: 8476708
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion. The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Masaru Kito, Kiyotaka Miyano, Shinji Mori, Ichiro Mizushima
  • Patent number: 8441042
    Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
  • Patent number: 8431994
    Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: April 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang
  • Patent number: 8389995
    Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 5, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
  • Patent number: 8349719
    Abstract: A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: January 8, 2013
    Assignee: SK Hynix Inc.
    Inventor: Tae Su Jang
  • Patent number: 8293627
    Abstract: The described system relates to a method for forming a layer of a mono-crystalline semiconductor material on a substrate, comprising providing a substrate, growing epitaxially a template comprising at least one monolayer of a semiconductor material on the substrate, thereafter depositing an amorphous layer of the semiconductor material on the template; performing a thermal treatment or a laser anneal, thereby converting substantially all of the amorphous layer of the semiconductor material into a mono-crystalline layer of the semiconductor material. According to an embodiment, the semiconductor material is Ge and the substrate is a Si substrate. The template is preferably a few monolayers thick.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: October 23, 2012
    Assignee: IMEC
    Inventor: Ruben Lieten
  • Patent number: 8288821
    Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alan Bernard Botula, David S. Collins, Alvin Jose Joseph, Howard Smith Landis, James Albert Slinkman
  • Publication number: 20120248536
    Abstract: The present disclosure provides various embodiments of a semiconductor device and method of fabricating the semiconductor device. An exemplary semiconductor device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate and a tuned, stressed metal gate layer disposed over the gate dielectric layer. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the semiconductor substrate having different surface characteristics. In an example, the gate stack is disposed over a portion of a fin of the semiconductor substrate, and the fin has a varying thickness, providing a fin with a roughened surface. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the fin having different thicknesses.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 4, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Robert James Pascoe Lander
  • Patent number: 8269278
    Abstract: The semiconductor device with a ?-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the ?-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: September 18, 2012
    Assignee: National Sun Yat-Sen University
    Inventors: Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin
  • Patent number: 8242561
    Abstract: A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8222696
    Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: July 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
  • Publication number: 20120146144
    Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 14, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideto OHNUMA, Atsuo ISOBE, Hiromichi GODO
  • Publication number: 20120146102
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 14, 2012
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Patent number: 8174074
    Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chung-Hsun Lin, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8169024
    Abstract: A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A in-situ doped semiconductor material is formed on the first semiconductor layer adjacent to the gate structure. The dopant from the in-situ doped semiconductor material is then diffused into the first semiconductor layer to form extension regions. The method is also applicable to finFET structures.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kulkarni, Ghavam Shahidi
  • Patent number: 8138547
    Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
  • Publication number: 20120037991
    Abstract: A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material.
    Type: Application
    Filed: August 16, 2010
    Publication date: February 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Zhen Zhang
  • Publication number: 20120025311
    Abstract: A radiation-hardened semiconductor structure including an insulator material doped with at least one of a transition metal, a lanthanide, and an actinide, and a semiconductor material located over the insulator material. A semiconductor device including the radiation-hardened semiconductor structure is also disclosed as are method of forming the radiation-hardened semiconductor structure and the semiconductor device.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 2, 2012
    Applicant: ALLIANT TECHSYSTEMS INC.
    Inventor: John S. Canham
  • Patent number: 8097515
    Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • Publication number: 20110309446
    Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
    Type: Application
    Filed: June 16, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Publication number: 20110291188
    Abstract: A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Xuefeng Hua, Ying Zhang
  • Publication number: 20110272762
    Abstract: A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 10, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger A. Booth, JR., Kangguo Cheng, Joseph Ervin, Ali Khakifirooz, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8048728
    Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8008744
    Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.
    Type: Grant
    Filed: May 31, 2010
    Date of Patent: August 30, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn
  • Patent number: 7999251
    Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Guy M. Cohen, John A. Ott, Michael J. Rooks, Paul M. Solomon
  • Publication number: 20110193163
    Abstract: A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Publication number: 20110193166
    Abstract: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 11, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qingqing LIANG, Huilong ZHU, Zhijiong LUO, Haizhou YIN
  • Publication number: 20110169084
    Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bin YANG, Rohit PAL, Michael HARGROVE
  • Publication number: 20110163381
    Abstract: It is an object to provide a method for manufacturing a semiconductor substrate in which contamination of a semiconductor layer due to an impurity is prevented and the bonding strength between a support substrate and the semiconductor layer can be increased. An oxide film containing first halogen is formed on a surface of a semiconductor substrate, and the semiconductor substrate is irradiated with ions of second halogen, whereby a separation layer is formed and the second halogen is contained in a semiconductor substrate. Then, heat treatment is performed in a state in which the semiconductor substrate and the support substrate are superposed with an insulating surface containing hydrogen interposed therebetween, whereby part of the semiconductor substrate is separated along the separation layer, so that a semiconductor layer containing the second halogen is provided over the support substrate.
    Type: Application
    Filed: March 17, 2011
    Publication date: July 7, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20110156045
    Abstract: A crystal manufacturing apparatus capable of manufacturing a crystal in a desired position on a substrate is provided. A spring has one end fixed to a mount and the other end coupled to a magnetic body. The magnetic body has one end coupled to the spring and the other end coupled to a piston. A coil is wound around the magnetic body and electrically connected between a power supply circuit and a ground node (GND). The piston has a linear member inserted in a cylinder. The cylinder has a hollow columnar shape and a small hole at a bottom surface. The cylinder holds a silicon melt. A substrate is supported by an XY stage to be opposed to the small hole of the cylinder. The power supply circuit passes pulse shaped current through the coil to move the piston in an up-down direction (DR1). As a result, a droplet is discharged toward the substrate from the small hole at an initial speed of 1.02 m/s.
    Type: Application
    Filed: August 28, 2009
    Publication date: June 30, 2011
    Applicant: HIROSHIMA UNIVERSITY
    Inventors: Seiichiro Higashi, Naohiro Koba
  • Publication number: 20110133167
    Abstract: A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • Publication number: 20110115021
    Abstract: Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 19, 2011
    Applicant: International Business Machines Corporation
    Inventors: Robert H. Dennard, Marwan H. Khater, Leathen Shi, Jeng-Bang Yau
  • Publication number: 20110108918
    Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Haizhou Yin, Xinhui Wang, Kevin K. Chan, Zhibin Ren
  • Publication number: 20110062518
    Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
  • Publication number: 20110049627
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.
    Type: Application
    Filed: September 1, 2009
    Publication date: March 3, 2011
    Applicant: International Business Machines Corporation
    Inventors: LELAND CHANG, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20110049626
    Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
    Type: Application
    Filed: September 1, 2009
    Publication date: March 3, 2011
    Applicant: International Business Machines Corporation
    Inventors: CHUNG-HSUN LIN, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20110049624
    Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 3, 2011
    Applicant: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
  • Publication number: 20110042744
    Abstract: A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A in-situ doped semiconductor material is formed on the first semiconductor layer adjacent to the gate structure. The dopant from the in-situ doped semiconductor material is then diffused into the first semiconductor layer to form extension regions. The method is also applicable to finFET structures.
    Type: Application
    Filed: August 18, 2009
    Publication date: February 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kulkarni, Ghavam Shahidi
  • Patent number: 7884377
    Abstract: A light emitting device including: at least one light emitting stack including first and second conductivity type semiconductor layers and an active layer disposed there between, the light emitting stack having first and second surfaces and side surfaces interposed between the first and second surfaces; first and second contacts formed on the first and second surface of the light emitting stack, respectively; a first insulating layer formed on the second surface and the side surfaces of the light emitting stack; a conductive layer connected to the second contact and extended along one of the side surfaces of the light emitting stack to have an extension portion adjacent to the first surface; and a substrate structure formed to surround the side surfaces and the second surface of the light emitting stack.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: February 8, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Grigory Onushkin, Jin Hyun Lee, Myong Soo Cho, Pun Jae Choi
  • Patent number: 7872309
    Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 18, 2011
    Assignee: Sharp Labratories of America, Inc.
    Inventors: Paul J. Schuele, Mark A. Crowder, Apostolos T. Voutsas, Hidayat Kisdarjono
  • Publication number: 20100327357
    Abstract: A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers.
    Type: Application
    Filed: May 3, 2010
    Publication date: December 30, 2010
    Inventor: Tae Su Jang
  • Patent number: 7859055
    Abstract: To provide: a thin film transistor which can be operated with a low threshold and has a high transistor withstand voltage; a production method of the thin film transistor; and a semiconductor device, an active matrix substrate, and a display device, each including such a thin film transistor. The present invention is a thin film transistor including a semiconductor layer, a gate insulating film, a gate electrode on a substrate in this order, wherein a cross section of the semiconductor layer has a forward tapered shape; the gate insulating film covers a top surface and a side surface of the semiconductor layer; and the gate insulating film has a multilayer structure including a silicon oxide film on a semiconductor layer side and a film made of a material with a dielectric constant higher than a dielectric constant of silicon oxide on a gate electrode side; the gate insulating film satisfies 0.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: December 28, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Matsukizono, Tadayoshi Miyamoto
  • Publication number: 20100315115
    Abstract: A method of characterizing semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, subtracting Igb of BT dummy device from that of the BT SOI device to obtain Igb of a floating body (FB) SOI device, filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device, and analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances of the FB SOI device.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 16, 2010
    Inventors: Yue-Shiun Lee, Yuan-Chang Liu, Cheng-Hsiung Chen