Abstract: A method for manufacturing a thin film transistor having high electric characteristics with high productivity. In the method for forming a channel region of a dual-gate thin film transistor including a first gate electrode and a second gate electrode which faces the first gate electrode with the channel region provided therebetween, a first microcrystalline semiconductor film is formed under a first condition for forming a microcrystalline semiconductor film in which a space between crystal grains is filled with an amorphous semiconductor, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a second condition for promoting crystal growth.

Abstract: It is an object to provide a liquid crystal display device including a thin film transistor with high electric characteristics and high reliability. As for a liquid crystal display device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, and a channel protective layer which is formed over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film.

Abstract: This thin-film transistor includes adhesive strength enhancing films between a barrier film and electrode films. Each of the adhesive strength enhancing film is composed of two zones including (a) a pure copper zone that is formed on the electrode film side, and (b) a component concentrated zone that is formed in an interface portion contact with the barrier film, and that includes Cu, Ca, oxygen, and Si as constituents. In concentration distributions of Ca and oxygen in a thickness direction of the component concentrated zone, a maximum content of Ca of a Ca-containing peak is in a range of 5 to 20 at %, and a maximum content of oxygen of an oxygen-containing peak is in a range of 30 to 50 at %, respectively.

Abstract: A thin-film transistor (TFT) substrate includes a gate electrode, a gate insulation pattern, a channel pattern, a first organic insulation pattern, a source electrode and a drain electrode. The gate electrode is formed on a base substrate. The gate insulation pattern is formed on the gate electrode and is smaller than the gate electrode. The channel pattern is formed on the gate insulation pattern and the channel pattern is smaller than the gate electrode. The first organic insulation pattern is formed on the base substrate to cover the channel pattern, the gate insulation pattern and the gate electrode.

Abstract: A semiconductor device can easily reduce a leak current which flows when a reversely-staggered-type TFT element in which an active layer is made of polycrystalline semiconductor is turned off. The semiconductor device includes a reversely-staggered-type TFT element in which a semiconductor layer, a source electrode and a drain electrode are arranged on a surface of an insulation film, and a portion of the source electrode and a portion of the drain electrode respectively get over the semiconductor layer.

Abstract: A method of manufacturing a thin film transistor and a thin film transistor, the method including sequentially forming a gate insulating layer, an amorphous silicon layer and an insulating layer on an entire top surface of a substrate having a gate electrode; patterning the insulating layer to form an etch stopper; and patterning the amorphous silicon layer to form a semiconductor layer.

Abstract: In a thin film transistor, a gate insulating layer is formed on a gate electrode formed on an insulating substrate. Formed on the gate insulating layer is a semiconductor layer. Formed on the semiconductor layer are a source electrode and a drain electrode. A protective layer covers them, so that the semiconductor layer is blocked from an atmosphere. The semiconductor layer (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm3 to about 4E23 atoms/cm3. The source and the drain are connected with the silicon-rich channel layer.

Abstract: The present invention relates to a thin film transistor substrate and a method for fabricating the same, which can shorten a process time, prevent a scratch from taking place at an alignment film, and increase black luminance. The thin film transistor substrate includes a thin film transistor formed on a substrate, a protective film formed to flatten a step of the thin film transistor and have an uneven surface with repetitive projected patterns and recessed patterns, a pixel electrode formed on the protective film to maintain an uneven shape of the protective film, and an alignment film formed both on the protective film and the pixel electrode to maintain the uneven shapes of the protective film and the pixel electrode.

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.

Abstract: Disclosed is a thin film transistor including: a gate insulating layer covering a gate electrode; a microcrystalline semiconductor region over the gate insulating layer; a pair of amorphous semiconductor region over the microcrystalline semiconductor; a pair of impurity semiconductor layers over the amorphous semiconductor regions; and wirings over the impurity semiconductor layers. The microcrystalline semiconductor region has a surface having a projection and depression on the gate insulating layer side. The microcrystalline semiconductor region includes a first microcrystalline semiconductor region which is not covered with the amorphous regions and a second microcrystalline semiconductor region which is in contact with the amorphous semiconductor regions. A thickness d1 of the first microcrystalline semiconductor region is smaller than a thickness d2 of the second microcrystalline semiconductor region and d1 is greater than or equal to 30 nm.

Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

Abstract: A thin film transistor substrate, wherein the moving area of electrons between source and drain electrodes of a thin film transistor (TFT) is minimized, the moving distance of electrons is increased, and the sizes of capacitors defined by a gate electrode together with the respective source and drain electrodes are identical to each other so that an off current generated when the TFT is off can be minimized; a method of manufacturing the thin film transistor substrate; and a mask for manufacturing the thin film transistor substrate. Accordingly, it is possible to minimize an off current induced due to a phenomenon of electron trapping by light.

Abstract: An object is to provide a highly reliable transistor and a semiconductor device including the transistor. A semiconductor device including a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film over the gate insulating film; and a source electrode and a drain electrode over the oxide semiconductor film, in which activation energy of the oxide semiconductor film obtained from temperature dependence of a current (on-state current) flowing between the source electrode and the drain electrode when a voltage greater than or equal to a threshold voltage is applied to the gate electrode is greater than or equal to 0 meV and less than or equal to 25 meV, is provided.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: Provided are a display device, a thin-film transistor (TFT) substrate, and a method of fabricating the TFT substrate. The method includes: forming a gate electrode on a pixel region of a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film to overlap the gate electrode; forming a source electrode and a drain electrode to overlap the semiconductor layer and thus form a channel region; and forming a data insulating film on the source electrode and the drain electrode and patterning the data insulating film such that part of a contact hole formed in the data insulating film overlaps the channel region.

Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.

Abstract: A non-linear element (e.g., a diode) with small reverse saturation current is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and a third electrode provided in contact with the gate insulating film and adjacent to a side surface of the oxide semiconductor film with the gate insulating film interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrode is connected to the first electrode or the second electrode.

Abstract: It is an object to provide a thin film transistor with high speed operation, in which a large amount of current can flow when the thin film transistor is on and off-state current is extremely reduced when the thin film transistor is off. The thin film transistor is a vertical thin film transistor in which a channel formation region is formed using an oxide semiconductor film in which hydrogen is contained in an oxide semiconductor at a concentration of lower than or equal to 5×1019/cm3, preferably lower than or equal to 5×1018/cm3, more preferably lower than or equal to 5×1017/cm3, hydrogen or an OH group contained in the oxide semiconductor is/are removed, and carrier concentration is lower than or equal to 5×1014/cm3, preferably lower than or equal to 5×1012/cm3.

Abstract: A semiconductor device having a pair of impurity doped second semiconductor layers, formed on a first semiconductor layer having a channel formation region therein, an outer edge of the first semiconductor film being at least partly coextensive with an outer edge of the impurity doped second semiconductor layers. The semiconductor device further includes source and drain electrodes formed on the pair of impurity doped second semiconductor layers, wherein the pair of impurity doped second semiconductor layers extend beyond inner sides edges of the source and drain electrodes so that a stepped portion is formed from an upper surface of the source and drain electrodes to a surface of the first semiconductor film.

Abstract: A method of patterning a transparent conductive film adaptive for selectively etching a transparent conductive film without any mask processes, a thin film transistor for a display device using the same and a fabricating method thereof are disclosed. In the method of patterning the transparent conductive film, an inorganic material substrate is prepared. An organic material pattern is formed at a desired area of the inorganic material substrate. A thin film having a different crystallization rate depending upon said inorganic material and said organic material is formed. The thin film is selectively etched in accordance with said crystallization rate.

Abstract: A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

Abstract: The present invention relates to a thin-film transistor in a liquid crystal display device and a method of fabricating the same, and the thin-film transistor may be configured by including a first gate electrode formed on an insulating substrate; a first gate insulation film formed on the insulating substrate including the first gate electrode; an active layer formed on the first gate insulation film; source/drain electrodes formed on the active layer and arranged at both sides of the first gate electrode; a second gate insulation film formed on the active layer and the first gate insulation film including the source/drain electrodes and provided with a contact hole for exposing part of the drain electrode; a second gate electrode overlapped with the first gate electrode on the second gate insulation film; and a pixel electrode electrically connected to the drain electrode through the contact hole.

Abstract: A thin film transistor (TFT) and a method of fabricating the same are disclosed. The TFT includes a substrate, a gate electrode disposed over the substrate, a gate insulating layer disposed over the gate electrode, a semiconductor layer disposed over the gate insulating layer and including a polycrystalline silicon (poly-Si) layer, an ohmic contact layer disposed over a predetermined region of the semiconductor layer, an insulating interlayer disposed over substantially an entire surface of the substrate including the ohmic contact layer, and source and drain electrodes electrically connected to the ohmic contact layer through contact holes formed in the interlayer insulating layer. A barrier layer is interposed between the semiconductor layer and the ohmic contact layer. Thus, when an off-current of a bottom-gate-type TFT is controlled, degradation of characteristics due to a leakage current may be prevented using a simple process.

Abstract: A metallic wiring film, which is not exfoliated even when exposed to plasma of hydrogen, is provided. A metallic wiring film is constituted by an adhesion layer in which Al is added to copper and a metallic low-resistance layer which is disposed on the adhesion layer and made of pure copper. When a copper alloy including Al and oxygen are included in the adhesion layer and a source electrode and a drain electrode are formed from it, copper does not precipitate at an interface between the adhesion layer and the silicon layer even when being exposed to the hydrogen plasma, which prevents the occurrence of exfoliation between the adhesion layer and the silicon layer. If the amount of Al increases, since widths of the adhesion layer and the metallic low-resistance layer largely differ after etching, the maximum addition amount for permitting the etching to be performed is the upper limit.

Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.

Abstract: A production method of a semiconductor element having a channel includes forming a resist pattern film on a thin film formed on a substrate, and pattering the thin film by etching. The production method also includes forming a second resist pattern film by applying a fluid resist material inside a channel groove after channel etching or inside a resist groove formed above a channel region before channel etching. The production method may also include forming a gate electrode, a gate insulating film, a semiconductor film, and a conductive film on an insulating substrate. The method may include applying the fluid resist material inside the channel groove, thereby forming the second resist pattern film, and patterning the semiconductor film using at least the second resist pattern film.

Abstract: A thin film transistor substrate includes a substrate including a display area and a peripheral area surrounding the display area, gate lines formed on the substrate including gate electrodes, an auxiliary insulating layer formed on the gate lines, a gate insulating layer formed on the auxiliary insulating layer and the gate lines, a semiconductor layer formed on the gate insulating layer, data lines formed on the semiconductor layer including source electrodes and drain electrodes, a passivation layer formed on the data lines, pixel electrodes formed on the passivation layer and electrically connected to the drain electrode, wherein the boundary line of the auxiliary insulating layer is located at or within the boundary of the gate line.

Abstract: There is provided a TFT substrate including a gate electrode having a thick film part and a thin film part with a smaller film thickness than the thick film part, a semiconductor active film formed above the thick film part and the thin film part of the gate electrode, an ohmic contact film formed on an inside of the semiconductor active film and on the semiconductor active film corresponding to the thin film part on an outside of the thick film part, and an electrode film constituting a source electrode and a drain electrode, having a planar shape identical to or on an inside of the ohmic contact film, and formed on the ohmic contact film.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract: A distance (d1) from an edge of a first region (R) at places (D) where branch electrodes (4b) extending, which branch off from an electrode line (4a) of a second source/drain electrode (4), start to overlap with a first region (R) to the electrode line (4a) is 5 ?m or more. This realizes a TFT including a comb-shaped source/drain structure that enables easy repair of a source-drain leakage.

Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.

Abstract: The present invention relates to a thin film transistor substrate. The thin film transistor according to one embodiment of the present invention comprises: a gate wire and a data wire formed to cross each other on an insulating substrate and define a pixel area; a thin film transistor formed on the intersection of the gate wire and the data wire; an inorganic insulating layer covering the thin film transistor and having a surface that a prominence and depression pattern formed on; and a reflective layer provided on the prominence and depression pattern. Thus, the present invention provides a thin film transistor substrate which reduces the time required in the process and enhance the productivity.

Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.

Abstract: A thin film transistor array panel includes a substrate; a first gate line disposed on the substrate and including a gate electrode; a storage electrode disposed in a layer which is the same layer as a layer of the first gate line; a gate insulating layer disposed on the first gate line and the storage electrode; a semiconductor disposed on the gate insulating layer and including a channel portion; a data line disposed on the semiconductor and including a source electrode; a drain electrode disposed on the semiconductor and facing the source electrode; a passivation layer disposed on the gate insulating layer, the data line, and the drain electrode, the passivation layer including a contact hole which exposes a portion of the drain electrode; and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode through the contact hole, wherein the gate insulating layer and the passivation layer are interposed between the pixel electrode and the substrate except for a regio

Abstract: Disclosed is a method that includes: forming a gate electrode on a substrate, then forming an insulation layer so as to completely cover the gate electrode, thereafter forming a semiconductor layer on the insulation layer, and then forming a crystallization-inducing metal layer on the semiconductor layer; removing the part of at least the crystallization-inducing metal layer that is over a channel region of the semiconductor layer; forming source and drain electrodes at a location which is over source and drain regions respectively located at opposite sides with respect to the channel region of the semiconductor layer and is above the crystallization-inducing metal layer; and heating the crystallization-inducing metal layer so as to form a silicide layer of a crystallization-inducing metal.

Abstract: An electronic apparatus having a substrate with a bottom gate p-channel type thin film transistor; a resist pattern over the substrate; and a light shielding film operative to block light having a wavelength shorter than 260 nm over at least a channel part of said thin film transistor.

Abstract: Thin film transistors and arrays having controlled threshold voltage and improved ION/IOFF ratio are provided in this invention. In one embodiment, a thin film transistor having a first gate insulator of high breakdown field with positive fixed charges and a second gate insulator with negative fixed charges is provided; said negative fixed charges substantially compensate said positive fixed charges in order to reduce threshold voltage and OFF state threshold voltage of said transistor. In another embodiment, a thin film transistor having a first passivation layer with negative fixed charges is provided, the negative charges reduce substantially unwanted negative charges in the adjacent active channel and hence reduce the OFF state current and increase ION/IOFF ratio, which in turn reduce the threshold voltage of the transistor.

Abstract: [Object] To provide a method of producing a thin film transistor superior in productivity and capable of preventing variation in transistor characteristics among devices from occurring to improve carrier mobility, and a thin film transistor. [Solving Means] In a method of producing a thin-film transistor according to the present invention, a solid-state green laser is irradiated onto a channel portion of an amorphous silicon film using a source electrode film and a drain electrode film as masks, thereby improving mobility. Since the channel portion of the amorphous silicon film is crystallized by the irradiation of the solid-state green laser, laser oscillation characteristics can be more stable than in a conventional method that uses an excimer laser. Further, laser irradiation onto a large-size substrate at uniform output characteristics in plane becomes possible, with the result that a variation in crystallinity of channel portions among devices can be avoided.

Abstract: A thin film transistor array substrate for a liquid crystal display includes a substrate, and a gate line assembly formed on the substrate to receive gate signals. The gate line assembly has gate lines proceeding in the horizontal direction, and gate electrodes connected to the gate lines. A storage capacitor line assembly proceeds in the horizontal direction. A gate insulating layer is formed on the substrate while covering the gate lines and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer over the gate electrodes. A data line assembly is formed on the gate insulating layer. The data line assembly has data lines crossing over the gate lines to define pixel regions, source electrodes connected to the data lines while being placed on the semiconductor pattern, and drain electrodes facing the source electrodes around the gate electrodes while being placed on the semiconductor pattern.

Abstract: A TFT array substrate comprises an insulator base; a first metal layer on the insulator base, a first portion thereof forming a gate electrode of a TFT; a gate insulating layer overlying the first metal layer and the insulator base; an amorphous silicon layer and a first layer of conductive transparent material both on the gate insulating layer; a doped amorphous silicon layer positioned on the amorphous silicon layer; a second metal layer on the doped amorphous silicon layer and the first layer of conductive transparent material, a first portion thereof forming source and drain electrodes of the TFT; a passivation layer on the second metal layer; and a second layer of conductive transparent material on the passivation layer, a first portion thereof forming a pixel electrode, wherein the first layer of conductive transparent material forms a portion of a common electrode of the array substrate.

Abstract: A TFT (5) includes: a gate electrode (12a); a first semiconductor portion (14a) that overlaps the gate electrode (12a) having the gate insulating film (13) interposed therebetween; a source electrode (15a) and a drain electrode (15b) that overlap the gate electrode (12a) having the gate insulating film (13) and the first semiconductor portion (14a) interposed therebetween; a second semiconductor portion (14b) that overlaps the gate electrode (12a) between the gate insulating film (13) and the source electrode (15a); and a conductive portion (15c) that overlaps the gate electrode (12a) having the gate insulating film (13) and the second semiconductor portion (14b) interposed therebetween. The TFT (5) brings the source line (15a) and the pixel electrode (17) into conduction by a switching element that includes short-circuit portion at the source electrode (15a) and the drain electrode (15b), the second semiconductor portion (14b) and the conductive portion (15c).

Abstract: An array substrate for a liquid crystal display device includes gate and data lines crossing on a substrate, common lines parallel to and between the gate lines, thin film transistors at crossing portions of the gate and data lines, and a pixel electrode. The common lines define pixel regions, which are each divided into first and second regions by the corresponding gate line. The thin film transistors each include a gate electrode in a first direction, a semiconductor layer on the gate electrode, and source and drain electrodes on the semiconductor layer in a second direction. The source and drain electrodes cross the gate electrode in each of the first and second regions. The pixel electrode is connected to the drain electrode.

Abstract: The manufacturing method of the present invention is a manufacturing method for an active matrix substrate with use of photolithography. The method includes the steps of: (i) removing, in a region where each of terminal sections is to be formed in a non-display region (peripheral region), at least a part of a gate insulating film GI (first interlayer insulating layer) deposited on a gate metal film (first metal film), followed by depositing a source metal film (second metal film) so as to form a plurality of signal wirings (Step (2)); and (ii) etching, in a display region, a passivation film Pas (second interlayer insulating layer) deposited on a plurality of source wirings (signal wirings) and a semiconductor layer (i layer) formed into TFTs so that the passivation film Pas and the semiconductor layer (i layer) have a same pattern except a part of a drain electrode (16a) of each of the TFTs (Step (4)).

Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

Abstract: A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.

Abstract: An Aluminum-Nickel alloy wiring material includes Aluminum, Nickel, Cerium, and Boron. A thin film transistor includes the Aluminum-Nickel alloy wiring material. A sputtering target comprises Aluminum, Nickel, Cerium and Boron. A method of manufacturing a thin film transistor substrate comprises disposing a thin film transistor on a substrate, wherein the thin film transistor includes a wiring circuit layer comprising Aluminum, Nickel, Cerium, and Boron. The Nickel, Cerium and Boron satisfy the following inequalities; 0.5?X?5.0, 0.01?Y?1.0, and 0.01?Z?1.0, respectively, wherein X represents an atomic percentage of Nickel content, Y represents an atomic percentage of Cerium content, and Z represents an atomic percentage of Boron content.

Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.