Including Nitride (e.g., Gan) (epo) Patents (Class 257/E33.025)
  • Patent number: 10056263
    Abstract: A SiC wafer is processed by a laser beam having a wavelength that transmits SiC to form a peeling plane in a region of the wafer which corresponds to a device area of a first surface of the wafer. A plurality of devices demarcated by a plurality of intersecting projected dicing lines in the device area are formed on the first surface. An annular groove is formed on a second surface of the wafer which is opposite the first surface, in a boundary region of the wafer between the device area and an outer peripheral excessive area surrounding the device area. A portion of the wafer which is positioned radially inwardly of the annular groove is peeled from the peeling plane, thereby thinning the device area and forming an annular stiffener area on a region of the second surface which corresponds to the outer peripheral excessive area.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: August 21, 2018
    Assignee: DISCO CORPORATION
    Inventor: Katsuhiko Suzuki
  • Patent number: 9543469
    Abstract: A III nitride semiconductor epitaxial substrate having more excellent surface flatness is provided, in which the problems of crack formation and the double peaks in the shape of the EL spectrum are mitigated by employing appropriate conditions for Si doping on an AlN layer on a substrate; a III nitride semiconductor light emitting device; and methods of producing the same. A III nitride semiconductor epitaxial substrate has a substrate of which at least a surface portion is made of AlN, an undoped AlN layer formed on the substrate, an Si-doped AlN buffer layer formed on the undoped AlN layer, and a superlattice laminate formed on the Si-doped AlN buffer layer. The Si-doped AlN buffer layer has an Si concentration of 2.0×1019/cm3 or more and a thickness of 4 nm to 10 nm.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: January 10, 2017
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Masatoshi Iwata, Yoshikazu Ooshika
  • Patent number: 9040326
    Abstract: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 26, 2015
    Assignee: The Regents of the University of California
    Inventors: Hong Zhong, Anurag Tyagi, Kenneth J. Vampola, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 9024331
    Abstract: Disclosed is a semiconductor light emitting element (LC) provided with a substrate (110) having one surface on which plural hexagonal-pyramid-shaped protrusions (110b) are provided, a base layer (130) provided so as to be in contact with the surface on which the protrusions (110b) are provided, an n-type semiconductor layer (140) provided so as to be in contact with the base layer (130), a light emitting layer (150) provided so as to be in contact with the n-type semiconductor layer (140), and a p-type semiconductor layer (160) provided so as to be in contact with the light emitting layer (150). Each protrusion (110b) scatters light in lateral and oblique directions within the semiconductor light emitting element (LC). The protrusions are densely arranged on a substrate on which semiconductor layers are laminated, so that the light extraction efficiency is improved.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: May 5, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yohei Sakano
  • Patent number: 9023721
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Patent number: 9012921
    Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chao-Kun Lin, Li Yan, Chih-Wei Chuang
  • Patent number: 9012944
    Abstract: A light emitting device is provided. The light emitting device includes a first semiconductor layer, an uneven part on the first semiconductor layer, a first nonconductive layer including a plurality of clusters on the uneven part, a first substrate layer on the nonconductive layer, and a light emitting structure layer. The light emitting structure layer includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer on the first substrate layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: April 21, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Ho Sang Yoon, Sang Kyun Shim
  • Patent number: 9006013
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The method can include forming a nitride semiconductor layer including a light emitting layer on a first substrate having an unevenness, bonding the nitride layer to a second substrate, and separating the first substrate from the nitride layer by irradiating the nitride layer with light. The forming the nitride layer includes leaving a cavity in a space inside a depression of the unevenness while forming a thin film on the depression. The film includes a same material as part of the nitride layer. The separating includes causing the film to absorb part of the light so that intensity of the light applied to a portion of the nitride layer facing the depression is made lower than intensity of the light applied to a portion facing a protrusion of the unevenness.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Gotoda, Toshiyuki Oka, Shinya Nunoue, Kotaro Zaima, Hiroshi Ono, Hajime Nago
  • Patent number: 9006706
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting layer, a first intermediate layer, and a second intermediate layer. The n-type and p-type semiconductor layers include a nitride semiconductor. The light emitting layer is provided between the n-type and p-type semiconductor layers, and includes barrier layers and a well layer. A bandgap energy of the well layer is less than that of the barrier layers. The first intermediate layer is provided between the light emitting layer and the p-type semiconductor layer. A bandgap energy of the first intermediate layer is greater than that of the barrier layers. The second intermediate layer includes first and second portions. The first portion is in contact with a p-side barrier layer most proximal to the p-type semiconductor layer. The second portion is in contact with the first intermediate layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hung Hung, Yoshiyuki Harada, Jongil Hwang, Mitsuhiro Kushibe, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8999060
    Abstract: Millimeter-scale GaN single crystals in filamentary form, also known as GaN whiskers, grown from solution and a process for preparing the same at moderate temperatures and near atmospheric pressures are provided. GaN whiskers can be grown from a GaN source in a reaction vessel subjected to a temperature gradient at nitrogen pressure. The GaN source can be formed in situ as part of an exchange reaction or can be preexisting GaN material. The GaN source is dissolved in a solvent and precipitates out of the solution as millimeter-scale single crystal filaments as a result of the applied temperature gradient.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 7, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Boris N. Feigelson, Jennifer K. Hite, Francis J. Kub, Charles R. Eddy, Jr.
  • Patent number: 8994030
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a phosphor layer, and a transparent film. The semiconductor layer has a first face, a second face opposite to the first face, and a light emitting layer. The p-side electrode is provided on the second face in an area including the light emitting layer. The n-side electrode is provided on the second face in an area not including the light emitting layer. The phosphor layer is provided on the first face. The phosphor layer includes a transparent resin and phosphor dispersed in the transparent resin. The transparent film is provided on the phosphor layer and has an adhesiveness lower than an adhesiveness of the transparent resin.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Hideto Furuyama, Miyoko Shimada, Yosuke Akimoto, Hideyuki Tomizawa, Yoshiaki Sugizaki
  • Patent number: 8963123
    Abstract: A light-emitting diode includes a substrate, a stacked semiconductor structure on one side of the substrate, and a reflection layer on the other side of the substrate opposite to the stacked semiconductor structure. At least one contact electrode is disposed on the stacked semiconductor structure. The contact electrode includes a pad electrode and at least one finger electrode extending from the pad electrode. A light-guiding structure is disposed along the finger electrode.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 24, 2015
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Keng-Ying Liao, Yu-Hsuan Liu
  • Patent number: 8952389
    Abstract: A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-seop Kwak, Jae-hee Cho
  • Patent number: 8946775
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8941136
    Abstract: A semiconductor light emitting element includes a semiconductor stack part that includes a light emitting layer, a diffractive face that light emitted from the light emitting layer is incident to, convex portions or concave portions formed in a period which is longer than an optical wavelength of the light and is shorter than a coherent length of the light, wherein the diffractive face reflects incident light in multimode according to Bragg's condition of diffraction and transmits the incident light in multimode according to the Bragg's condition of diffraction, and a reflective face which reflects multimode light diffracted at the diffractive face and let the multimode light be incident to the diffractive face again. The semiconductor stack part is formed on the diffractive face.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: January 27, 2015
    Assignee: El-Seed Corporation
    Inventors: Satoshi Kamiyama, Motoaki Iwaya, Hiroshi Amano, Isamu Akasaki, Toshiyuki Kondo, Fumiharu Teramae, Tsukasa Kitano, Atsushi Suzuki
  • Patent number: 8928017
    Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-hee Chae, Young-soo Park, Bok-ki Min, Jun-youn Kim, Hyun-gi Hong
  • Patent number: 8916906
    Abstract: A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (BxAl1-xN) and an upper layer of GaN, for which 0.35?x?0.45. The BAlN forms a wurtzite-type crystal with a cell unit length about two-thirds of a silicon cell unit length on a Si(111) surface. The C-plane of the BAlN crystal has approximately one atom of boron for each two atoms of aluminum. Across the entire wafer substantially only nitrogen atoms of BAlN form bonds to the Si(111) surface, and substantially no aluminum or boron atoms of the BAlN are present in a bottom-most plane of atoms of the BAlN. A method of making the BAlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and triethylboron and then a subsequent amount of ammonia through the chamber.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: William E. Fenwick
  • Patent number: 8912020
    Abstract: A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8896017
    Abstract: A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: November 25, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jong Lam Lee, In-kwon Jeong, Myung Cheol Yoo
  • Patent number: 8890195
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8878213
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8872227
    Abstract: A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: October 28, 2014
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Umeda, Yoshiharu Anda, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: 8872308
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8866164
    Abstract: A semiconductor light emitting device having a light emitting structure including at least one first conductive GaN based semiconductor layer, an active layer above the at least one first conductive GaN based semiconductor layer, and at least one second conductive GaN based semiconductor layer above the active layer, a plurality of patterns disposed from the at least one second conductive GaN based semiconductor layer through a portion of the at least one first conductive GaN based semiconductor layer, and an insulating member on the plurality of patterns. The plurality of patterns include a lower part contacting with the light emitting structure and a upper part contacting with the light emitting structure. A first base angle of the lower part is different from the second base angle of the upper part.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: October 21, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sang Youl Lee
  • Patent number: 8860070
    Abstract: The present disclosure provides a vertical GaN-based semiconductor diode and a method of manufacturing the same. The GaN-based ?i-V group semiconductor device includes a substrate, a p-type ohmic electrode layer on the substrate, a p-type GaN-based ?i-V group compound semiconductor layer on the p-type ohmic electrode layer, an n-type GaN-based ?i-V group compound semiconductor layer on the p-type GaN-based ?i-V group compound semiconductor layer, and an n-type ohmic electrode layer on the n-type GaN-based IE-V group compound semiconductor layer. The p-type ohmic electrode layer is an Ag-based highly reflective electrode having a high reflectivity of 70% or more, and a surface of the n-type GaN-based E-V group compound semiconductor layer is subjected to at least one of a process of forming photonic crystals and a process of surface roughening.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: October 14, 2014
    Assignees: Seoul Viosys Co., Ltd., Pohang University of Science and Technology Academy-Industry Foundaton
    Inventor: Jong Lam Lee
  • Patent number: 8853668
    Abstract: A light emitting device comprises a first layer having an n-type Group III-V semiconductor, a second layer adjacent to the first layer, the second layer comprising an active material that generates light upon the recombination of electrons and holes. The active material in some cases has one or more V-pits at a density between about 1 V-pit/?m2 and 30 V-pits/?m2. The light emitting device includes a third layer adjacent to the second layer, the third layer comprising a p-type Group III-V semiconductor.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jeff Ramer, Steve Ting
  • Patent number: 8835200
    Abstract: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: September 16, 2014
    Assignee: The Regents of the University of California
    Inventors: Hong Zhong, Anurag Tyagi, Kenneth J. Vampola, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8835938
    Abstract: There is provided a nitride semiconductor light-emitting element including a transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the transparent conductor. There is also provided a nitride semiconductor light-emitting element including a first transparent conductor, a metal layer, a second transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the metal layer, the second transparent conductor, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the first transparent conductor.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: September 16, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshio Hata
  • Patent number: 8835930
    Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Patent number: 8828752
    Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 9, 2014
    Assignee: Manutius IP Inc.
    Inventor: Steve Ting
  • Patent number: 8829651
    Abstract: A nitride-based semiconductor substrate has a diameter of 25 mm or more, a thickness of 250 micrometers or more, a n-type carrier concentration of 1.2×1018 cm?3 or more and 3×1019 cm?3 or less, and a thermal conductivity of 1.2 W/cmK or more and 3.5 W/cmK or less. Alternatively, the substrate has an electron mobility ? [cm2/Vs] of more than a value represented by loge ?=17.7?0.288 loge n and less than a value represented by loge ?=18.5?0.288 loge n, where the substrate has a n-type carrier concentration n [cm?3] that is 1.2×1018 cm?3 or more and 3×1019 cm?3 or less.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: September 9, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventor: Yuichi Oshima
  • Patent number: 8829658
    Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi Arakawa, Michimasa Miyanaga, Takashi Sakurada, Yoshiyuki Yamamoto, Hideaki Nakahata
  • Patent number: 8829559
    Abstract: In a nitride semiconductor light-emitting device having an n-side and a p-side electrode pad formed on the same side of a substrate wherein current distribution in the light-emitting device is improved by forming branch electrodes extended from the p-side electrode pad (and the n-side electrode pad), when sheet resistance values of n-side and p-side layers in the device are low enough, contact resistance between a p-type nitride semiconductor layer and a current diffusion layer of a transparent conductive film formed thereon is reduced and in-plane distribution of the sheet resistance is made uniform whereby improving the optical output, by increasing in a prescribed condition the sheet resistance value of the current diffusion layer.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 9, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yufeng Weng, Michael Brockley
  • Patent number: 8823033
    Abstract: A nitride semiconductor ultraviolet light-emitting device includes at least one first conductivity-type nitride semiconductor layer, a nitride semiconductor emission layer, at least one second conductivity-type nitride semiconductor layer and a transparent conductive film of crystallized Mgx1Zn1-x1O (0<x1<1) that can transmit 75% or more of light emitted from the emission layer, sequentially stacked in this order on a support substrate.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 2, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shuichiro Yamamoto, Shuichi Hirukawa, Masataka Ohta
  • Patent number: 8809898
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 19, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jong Lam Lee, Inkwon Jeong, Myung Cheol Yoo
  • Patent number: 8802471
    Abstract: Techniques for manufacturing optical devices are disclosed. More particularly, light emitting diodes and in particular to ohmic contacts for light emitting diodes are disclosed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 12, 2014
    Assignee: Soraa, Inc.
    Inventors: Michael J. Cich, Kenneth John Thomson
  • Patent number: 8796665
    Abstract: Solid state radiation transducer (SSRT) assemblies and method for making SSRT assemblies. In one embodiment, a SSRT assembly comprises a first substrate having an epitaxial growth material and a radiation transducer on the first substrate. The radiation transducer can have a first semiconductor material grown on the first substrate, a second semiconductor material, and an active region between the first and second semiconductor materials. The SSRT can also have a first contact electrically coupled to the first semiconductor material and a second contact electrically coupled to the second semiconductor material. The first substrate has an opening through which radiation can pass to and/or from the first semiconductor material.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Anton J. De Villiers
  • Patent number: 8785965
    Abstract: A nitride-based semiconductor light-emitting device according to the present invention has a nitride-based semiconductor multilayer structure 50. The nitride-based semiconductor multilayer structure 50 includes: an active layer 32 including an AlaInbGacN crystal layer (where a+b+c=1, a?0, b?0 and c?0); an AldGaeN overflow suppressing layer 36 (where d+e=1, d>0, and e?0); and an AlfGagN layer 38 (where f+g=1, f?0, g?0 and f<d). The AldGaeN overflow suppressing layer 36 is arranged between the active layer 32 and the AlfGagN layer 38. And the AldGaeN overflow suppressing layer 36 includes an In-doped layer that is doped with In at a concentration of 1×1016 atms/cm3 to 1×1019 atms/cm3.
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: July 22, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Ryou Kato
  • Patent number: 8772064
    Abstract: A method of fabricating a III-nitride semiconductor laser device includes: preparing a substrate having a hexagonal III-nitride semiconductor and having a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, the laser structure including a substrate and a semiconductor region formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal III-nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: July 8, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Patent number: 8728236
    Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: May 20, 2014
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo
  • Patent number: 8729578
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The second semiconductor layer is provided on a [0001]-direction side of the first semiconductor layer. The light emitting layer includes a first well layer, a second well layer and a first barrier layer. An In composition ratio of the barrier layer is lower than that of the first well layer and the second well layer. The barrier layer includes a first portion and a second portion. The second portion has a first region and a second region. The first region has a first In composition ratio higher than that of the first portion. The second region is provided between the first region and the first well layer. The second region has a second In composition ratio lower than the first In composition ratio.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hajime Nago, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8729563
    Abstract: Solid state lighting (SSL) devices and methods are disclosed. A particular method includes forming an SSL formation structure having a CTE, selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material based at least in part on the second material having a CTE less than the first material CTE. The intelayer structure is formed over the SSL formation structure e.g., with a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The CTE difference between the first and second materials can counteract a force placed on the formation structure by the first material. Particular formation structures can have an off-cut angle with a non-zero value of up to about 4.5 degrees.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Ji-Soo Park
  • Patent number: 8729575
    Abstract: The semiconductor light emitting device according to an embodiment includes an N-type nitride semiconductor layer, a nitride semiconductor active layer disposed on the N-type nitride semiconductor layer, and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor layer includes an aluminum gallium nitride layer. The indium concentration in the aluminum gallium nitride layer is between 1E18 atoms/cm3 and 1E20 atoms/cm3 inclusive. The carbon concentration is equal to or less than 6E17 atoms/cm3. Where the magnesium concentration is denoted by X and the acceptor concentration is denoted by Y, Y>{(?5.35e19)2?(X?2.70e19)2}1/2?4.63e19 holds.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Hung Hung, Yasushi Hattori, Rei Hashimoto, Shinji Saito, Masaki Tohyama, Shinya Nunoue
  • Patent number: 8729564
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a barrier metal layer, a first metal pillar, a second metal pillar, and a resin. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode is provided on the second major surface of the semiconductor layer. The second electrode is provided on the second major surface of the semiconductor layer and includes a silver layer. The insulating film is provided on the second major surface side of the semiconductor layer. The barrier metal layer is provided between the second electrode and the insulating film and between the second electrode and the second interconnection to cover the second electrode.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 8698163
    Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventor: Steve Ting
  • Patent number: 8685772
    Abstract: There is provided a method of manufacturing a light emitting diode and a light emitting diode manufactured by the same. The method includes growing a first conductivity type nitride semiconductor layer and an undoped nitride semiconductor layer on a substrate sequentially in a first reaction chamber; transferring the substrate having the first conductivity type nitride semiconductor layer and the undoped nitride semiconductor layer grown thereon to a second reaction chamber; growing an additional first conductivity type nitride semiconductor layer on the undoped nitride semiconductor layer in the second reaction chamber; growing an active layer on the additional first conductivity type nitride semiconductor layer; and growing a second conductivity type nitride semiconductor layer on the active layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Ju Lee, Heon Ho Lee, Hyun Wook Shim, Young Sun Kim
  • Patent number: 8686397
    Abstract: A light emitting diode structure of (Al,Ga,In)N thin films grown on a gallium nitride (GaN) semipolar substrate by metal organic chemical vapor deposition (MOCVD) that exhibits reduced droop. The device structure includes a quantum well (QW) active region of two or more periods, n-type superlattice layers (n-SLs) located below the QW active region, and p-type superlattice layers (p-SLs) above the QW active region. The present invention also encompasses a method of fabricating such a device.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 1, 2014
    Assignee: The Regents of the University of California
    Inventors: Shuji Nakamura, Steven P. DenBaars, Shinichi Tanaka, Daniel F. Feezell, Yuji Zhao, Chih-Chien Pan
  • Patent number: 8685767
    Abstract: A double-metallic deposition process is used whereby adjacent layers of different metals are deposited on a substrate. The surface plasmon frequency of a base layer of a first metal is tuned by the surface plasmon frequency of a second layer of a second metal formed thereon. The amount of tuning is dependent upon the thickness of the metallic layers, and thus tuning can be achieved by varying the thicknesses of one or both of the metallic layers. In a preferred embodiment directed to enhanced LED technology in the green spectrum regime, a double-metallic Au/Ag layer comprising a base layer of gold (Au) followed by a second layer of silver (Ag) formed thereon is deposited on top of InGaN/GaN quantum wells (QWs) on a sapphire/GaN substrate.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: April 1, 2014
    Assignee: Lehigh University
    Inventors: Nelson Tansu, Hongping Zhao, Jing Zhang, Guangyu Liu
  • Patent number: 8686455
    Abstract: A composite substrate for the formation of a light-emitting device, ensuring that a high-quality nitride-based light-emitting diode can be easily formed on its top surface and the obtained substrate-attached light-emitting diode functions as a light-emitting device capable of emitting light for an arbitrary color such as white, is provided.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 1, 2014
    Assignees: Ube Industries, Ltd., Riken
    Inventors: Yasuyuki Ichizono, Hideki Hirayama
  • Patent number: 8686430
    Abstract: A buffer layer of zinc telluride (ZnTe) or titanium dioxide (TiO2) is formed directly on a silicon substrate. Optionally, a layer of AlN is then formed as a second layer of the buffer layer. A template layer of GaN is then formed over the buffer layer. An epitaxial LED structure for a GaN-based blue LED is formed over the template layer, thereby forming a first multilayer structure. A conductive carrier is then bonded to the first multilayer structure. The silicon substrate and the buffer layer are then removed, thereby forming a second multilayer structure. Electrodes are formed on the second multilayer structure, and the structure is singulated to form blue LED devices.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventor: Zhen Chen