By Using Wire As Conductive Path Patents (Class 29/850)
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Patent number: 6490785Abstract: In a manufacturing apparatus of a wire harness in which pallet P, on which a plurality of connectors C are juxtaposed, is moved by a pallet feeding section 1 and a pressure-contact terminal of connector C is automatically positioned at a pressure-contact position under a pressure-contact head section 4, an electric wire “a” is automatically set at a pressure-contact terminal of connector C by an electric wire supply section 2 and an electric wire setting section 3, and cover L is automatically set on connector C by a cover mounting section 5. A type and position of the electric wire “a” to be arranged and the height of press-fitting of the electric wire into the pressure-contact terminal are controlled by a program, and the operation and state are checked by a sensor.Type: GrantFiled: September 7, 1999Date of Patent: December 10, 2002Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.Inventor: Toshio Kometani
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Patent number: 6481101Abstract: A method for producing a cable harness includes the step of applying an essentially strip-shaped base layer having a plastic thixotropic material to an assembly support. A plurality of essentially parallel adjacent wires are fixed to the base layer. A cover layer of plastic material is applied onto the base layer. The cover layer is subsequently treated so that the plastic material envelops the wires, adheres to the base layer and changes to a more solid consistency.Type: GrantFiled: August 13, 1999Date of Patent: November 19, 2002Assignee: Leoni Bordnetz-Systeme GmbH & Co. KGInventor: Gerhard Reichinger
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Patent number: 6481100Abstract: A method of manufacturing a wiring board comprising the steps of winding an electrical wire around a insulating plate having a number of electrical wire grooves for placing an electrical wire therein and a number of terminal grooves formed at positions corresponding to the electrical wire grooves in which the attached pressure connection terminal is connected to the electrical wire making use of the electrical wire grooves; cutting the electrical wire wound around the insulating plate at desired positions; and attaching the pressure connection terminal at a desired position in the number of terminal grooves, a wiring board, and an electrical connection box manufactured by accommodating the wiring box in a casing.Type: GrantFiled: January 26, 2001Date of Patent: November 19, 2002Assignee: The Furukawa Electric Co., Ltd.Inventors: Masakazu Murakami, Mitsuo Tanaka, Tatsuo Satori
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Publication number: 20020166696Abstract: A method and structure to repair or modify a land grid array (LGA) interface mounted on a printed circuit card. The land grid array interface has a plurality of contact pads on a first surface of the printed circuit card, each contact pad is connected to at least one electronic component by a conductor. The method includes, for a preselected one of the contact pads to be replaced, drilling a first hole through printed circuit card at a predetermined location and having a first diameter predetermined to be sufficient to electrically isolate the preselected contact pad from all circuits contained in or on the printed circuit card. If any of the preselected contact pad or any conductor material directly attached to it remains attached to the first surface, it is delaminated, thereby separating it from the first surface of the printed circuit card.Type: ApplicationFiled: May 10, 2001Publication date: November 14, 2002Applicant: International Business Machines CorporationInventors: Bruce J. Chamberlin, Mark Kenneth Hoffmeyer, Wai Mon Ma, Arch F. Nuttall, James R. Stack
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Patent number: 6415504Abstract: A method for altering a circuit pattern of a printed-circuit board includes the steps of removing a portion of the printed-circuit board so that the circuit pattern inside the printed-circuit board is exposed, and connecting an exposed portion of the circuit pattern to another portion of the printed-circuit board by a conductive body so that a circuit path is formed between the exposed portion of the circuit pattern and the other portion of the printed-circuit board.Type: GrantFiled: September 9, 1996Date of Patent: July 9, 2002Assignee: Fujitsu LimitedInventor: Shinji Matsuda
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Patent number: 6385845Abstract: A wiring method for an electrical wire 3 is provided. In the resultant wiring structure, an insulating base member 11 is provided with a plurality of projections 12 formed along a designated wiring route. Each projection 12 is provided with a dented top for receiving the wire 3. By using an ultrasonic welding machine, the wire 3 is welded on the projections 12 in order, while wiring the wire 3 on the insulating base member 11. The insulating base member 11 has a plurality of shelf portions providing a three-dimensional structure.Type: GrantFiled: February 21, 2001Date of Patent: May 14, 2002Assignee: Yazaki CorporationInventor: Toshiyuki Mori
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Patent number: 6350132Abstract: What is disclosed is a elastomeric connector and the associated method used to manufacture the elastomeric connector. The elastomeric connector includes a segment of a dielectric substrate having a top surface and a bottom surface. A plurality of conductive elements are positioned within the dielectric substrate in a predetermined pattern. Portions of the conductive elements lay exposed on the top surface and the bottom surface of the dielectric substrate within the selected pattern. Accordingly, any contacts that abut against the top surface and the bottom surface of the elastomeric connector will be electrically interconnected by the conductive wire. Each of the conductive elements is configured in a manner that prevents the dielectric substrate from enveloping the conductive elements at the points where they enter the dielectric substrate.Type: GrantFiled: November 29, 1999Date of Patent: February 26, 2002Inventor: George F. Glatts, III
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Patent number: 6313395Abstract: An interconnect structure for use with solar cells and like devices which are subject to compressive and/or expansive forces through packaging or in application comprises a flattened spiral of a metal strip. The interconnect is fabricated by first providing a length of metal strip, wrapping the metal strip around a cylindrical or flat mandrel or otherwise folded in a helical pattern, removing the mandrel, and then flattening the metal strip to reduce thickness of the interconnect.Type: GrantFiled: April 24, 2000Date of Patent: November 6, 2001Assignee: SunPower CorporationInventors: Richard A. Crane, Matthew B. Piper, Shandor G. Daroczi
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Patent number: 6295720Abstract: Method for manufacturing a coil arrangement with a plurality of winding wire regions (54, 55, 56) constructed in superimposed winding wire planes in a winding tool (28) with the following method steps: fixing of the winding wire (53) in a first wire holding device (39) at the circumferential edge of a basic matrix (21), rotation of the winding tool (28) so as to lay the winding wire (53) against an additional matrix (36) arranged on the basic matrix (21) of the winding tool (28) and formation of a first winding wire region (55) arranged on the surface (26) of the basic matrix, closure of the winding tool (28) by displacing a brace (48) towards the matrix surface (26) of the basic matrix (21) and rotation of the winding tool (28) so as to lay the winding wire (53) on the winding circumference (24) of the basic matrix (21) and formation of a further winding wire region as coil element (54), fixing of the coil element (54) and rotation of the winding tool (28) with brace (48) at a distance from the matrix suType: GrantFiled: February 26, 1999Date of Patent: October 2, 2001Inventors: David Finn, Manfred Rietzler
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Patent number: 6286208Abstract: A structure of an enhanced durability interconnector to reliably interconnect modules having high density type contacts, such as found in modules having solder ball connections (SBC), to a connecting article such as a printed circuit board. The structure comprising a means to provide the SBC type contact a mating surface having a wide contact area. Furthermore, the electrical connecting medium within the interconnector, which is embedded in an elastomeric material to provide compliance, is strengthened by using two or more embedded wires in combination for each wide contact area contact. The interconnector is incorporated into a fixture to compress the interconnector between the SBC module and the connecting article. The fixture having further capability to align the connections, control the compression pressure and to prevent over-compression.Type: GrantFiled: October 28, 1996Date of Patent: September 11, 2001Assignee: International Business Machines CorporationInventors: Da-Yuan Shih, Paul Lauro, Keith Edward Fogel, Brian Beaman, Maurice Norcott
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Patent number: 6282780Abstract: In a bump forming method and its forming apparatus, a torch is made to approach a bottom end of a wire extended from a capillary tool to form a ball, thereafter the wire is held by first clampers to lower the capillary tool, and the ball is inserted into the bottom end of the central hole of the capillary tool. Then, the wire is held by the first clampers so that it does not lower and cut by lowering of the capillary tool. Moreover, the capillary tool is further lowered and the ball is pressed against the electrode of a workpiece to bond the ball to the electrode to form a bump. A tail protruded from the bump is crushed by pressing a pressing jig against the tail to make the height of the bump uniform. Thereby, the ball is firmly bonded to the electrode and the joint surface between the ball and the electrode is not damaged.Type: GrantFiled: February 6, 1997Date of Patent: September 4, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eisuke Waki, Tsuyoshi Takata, Hiroshi Haji
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Publication number: 20010010121Abstract: A method of manufacturing a wiring board comprising the steps of winding an electrical wire around a insulating plate having a number of electrical wire grooves for placing an electrical wire therein and a number of terminal grooves formed at positions corresponding to the electrical wire grooves in which the attached pressure connection terminal is connected to the electrical wire making use of the electrical wire grooves; cutting the electrical wire wound around the insulating plate at desired positions; and attaching the pressure connection terminal at a desired position in the number of terminal grooves, a wiring board, and an electrical connection box manufactured by accommodating the wiring box in a casing.Type: ApplicationFiled: January 26, 2001Publication date: August 2, 2001Inventors: Masakazu Murakami, Mitsuo Tanaka, Tatsuo Satori
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Patent number: 6255581Abstract: A surface mount technology compatible electromagnetic interference (EMI) gasket assembly includes an electrically conductive gasket material, a solderable electrically conductive support layer, and an adhesive or other mechanical assembly for affixing the electrically conductive gasket material to the support layer.Type: GrantFiled: March 31, 1998Date of Patent: July 3, 2001Assignee: Gore Enterprise Holdings, Inc.Inventors: Bradley E. Reis, David R. King
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Patent number: 6172879Abstract: A method for isolating a pin of a ball grid array (BGA) device mounted on a printed circuit board, and routing the signal carried by the isolated pin to an alternate location. The BGA device pin is isolated by removing the solder ball to expose the device pad. A rework or engineering wire is then soldered to the BGA device pad using a high temperature solder. The rework wire is then routed between the other solder pads to the edge of the BGA device package. The BGA device is then reflowed at a temperature lower than the reflow temperature of the high temperature solder. The rework wire is used to route the signal carried by the isolated BGA pin to an alternate location. The present invention provides for higher process yields than conventional rework processes.Type: GrantFiled: June 30, 1998Date of Patent: January 9, 2001Assignee: Sun Microsystems, Inc.Inventors: Michael C. Cilia, Don Nguyen, Gurpreet S. Dayal
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Patent number: 6137054Abstract: A wire-circuit sheet includes: a resin sheet with circuit connecting holes, wires lying across the circuit connecting holes , and at least on cutting hole to punch the resin sheet so as to cut simultaneously the wires. Further, a wire-circuit sheet and its manufacturing method include: a resin sheet on which a plurality of wires lie as crossing or coming close to each other, cutting holes being provided at the crossing or close points of the plurality of wires to cut off the wires and the sheet together, and the wires being fixed and sandwiched in between laminated resin sheets with a sticky surface.Type: GrantFiled: January 24, 1995Date of Patent: October 24, 2000Assignee: Yazaki CorporationInventors: Kouichi Uezono, Keiichi Ozaki, Sanae Kato, Akira Sugiyama
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Patent number: 6111407Abstract: A method of producing a magnetic field sensor, whose sensor element is formed by at least one piece of wire comprising amorphous or nanocrystalline ferromagnetic material, whose electrical impedance is dependent on the magnetic field. The piece of wire is connected by an electrical terminal of nonferromagnetic metal. The ends of the at least one piece of wire are press-fitted into two spaced-apart conductors of nonferromagnetic metal, in particular copper.Type: GrantFiled: February 25, 1998Date of Patent: August 29, 2000Assignee: Securiton General Control Systems Gesellschaft m.b.H.Inventors: Hans Hauser, Johann Nicolics, Herbert Newald, Horst Bruggraber
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Patent number: 6081999Abstract: A wire-circuit sheet includes; a resin sheet with circuit connecting holes, wires lying across the circuit connecting holes, and at least one cutting hole to punch the resin sheet so as to cut simultaneously the wires. Further, a wire-circuit sheet and its manufacturing method include; a resin sheet on which a plurality of wires lie as crossing or coming close to each other, cutting of holes being provided at the crossing or close points of the plurality of wires to cut off the wires and the sheet together, and the wires being fixed and sandwiched in between laminated resin sheets with a sticky surface.Type: GrantFiled: December 14, 1998Date of Patent: July 4, 2000Assignee: Yazaki CorporationInventors: Kouichi Uezono, Keiichi Ozaki, Sanae Kato, Akira Sugiyama
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Patent number: 6078500Abstract: A structure for packaging an electronic device.Type: GrantFiled: May 12, 1998Date of Patent: June 20, 2000Assignee: International Business Machines Inc.Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Da-Yuan Shih
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Patent number: 6035530Abstract: A method for manufacturing an interconnect. A substrate having a first dielectric layer and a barrier layer formed thereon is provided. A plurality of conductive wires is formed on the barrier layer. A second dielectric layer is formed on the barrier layer exposed by the conductive wires, wherein the second dielectric layer has a surface level between the top surfaces and the bottom surfaces of the conductive wires. A spacer is formed on each portion of the sidewalls of the conductive wires exposed by the second dielectric layer, wherein there is a gap between two adjacent spacers. The second dielectric layer is removed. A third dielectric layer is formed on the conductive wires, the spacer, the sidewalls of the conductive wires and the portion of the barrier layer exposed by the conductive wires and fills the gap to form an air cavity between the conductive wires under the spacer.Type: GrantFiled: May 6, 1999Date of Patent: March 14, 2000Assignee: United Semiconductor Corp.Inventor: Gary Hong
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Patent number: 5987743Abstract: An automatic wiring device comprises an initial wiring unit for performing initial wiring processing on the coordinate plane surface for wiring arrangement to be processed, a short cost value setting unit for setting a cost value on each unit cell arranged on the coordinate plane surface for wiring arrangement in such a way that the cost value of the unit cell on the connected wiring in the vicinity of the terminals of the connected wiring is set larger than the cost values of any other unit cells when there remains a terminal pair unconnected in the wiring processing by the initial wiring unit, and a peeling and rewiring unit for performing wiring processing by the cost-attached labyrinth method, using the set cost values, and if peeling off another wiring in the above wiring processing, performing rewiring processing for connecting a terminal pair getting unconnected owing to the wiring being peeled off.Type: GrantFiled: April 24, 1997Date of Patent: November 23, 1999Assignee: NEC CorporationInventor: Nobuyasu Yui
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Patent number: 5937515Abstract: A method of manufacturing electronic circuitry and the resulting hardware is described in which a conduction plate is formed achieving separate electrical conducting paths for application specific signals is engaged with an electronic circuit package containing a wide range of elements including one or more integrated circuits, chip packages, multichip modules printed circuit boards and cables. One or more of these elements are assembled into the circuit package where all or a major portion of the element conductors are routed to terminals positioned for electrical connection between the circuit apparatus and the electrical conduction plate. The conduction plate completes the electrical interconnection of the circuit package by providing the application specific conduction paths, using various techniques for creating electrical conduction, such as severing segments of a generalized conductive grid to establish desired conduction paths.Type: GrantFiled: November 17, 1997Date of Patent: August 17, 1999Inventor: Morgan T. Johnson
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Patent number: 5917707Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.Type: GrantFiled: November 15, 1994Date of Patent: June 29, 1999Assignee: FormFactor, Inc.Inventors: Igor Y. Khandros, Gaetan L. Mathieu
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Patent number: 5890284Abstract: In aspect, the present invention is directed to a method of modifying a circuit board having at least one Ball Grid Array (BGA). The method includes removing the via portion of the BGA pad from the circuit board to sever the connection between the via and the circuit, attaching the pad connector to the circuit board, and connecting the pad connector to the circuit of the circuit board.Type: GrantFiled: November 25, 1997Date of Patent: April 6, 1999Assignee: International Business Machines CorporationInventors: Richard L. Chartrand, Wai-Mon Ma, Roger A. Stinemire
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Patent number: 5832602Abstract: A wire-circuit sheet comprising; a resin sheet with circuit connecting holes, wires lying across the circuit connecting holes, and a cutting holes to punch the resin sheet so as to cut simultaneously the wires. Further, a wire-circuit sheet and its manufacturing method comprising; a resin sheet on which a plurality of wires lie as crossing or coming close to each other, cutting holes being provided at the crossing or close points of the plurality of wires to cut off the wires and the sheet together, and the wires being fixed and sandwiched in between laminated resin sheets with a sticky surface.Type: GrantFiled: December 23, 1996Date of Patent: November 10, 1998Assignee: Yazaki CorporationInventors: Kouichi Uezono, Keiichi Ozaki, Sanae Kato, Akira Sugiyama
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Patent number: 5808241Abstract: A thin film transmission line, delay line constructed on a ceramic substrate. A serpentine, transmission line conductor and a surrounding, coplanar border ground are plated in registry onto the substrate. Discrete ground paths which project from the border are interspersed between the conductor windings to electrically shield adjacent windings. A hard coat epoxy resin covers the signal layer, which may support a sputtered ground plane that is connected to the border ground. An alternative delay line provides overlying ground fingers within the dielectric covering layer which are aligned to the channel spaces between the conductor windings. Both assemblies provide an increased number of conductor lines per chip. Edge coupled terminations are provided at the substrate to accommodate multi-layer assemblies of the delay line and/or circuit terminations.Type: GrantFiled: July 29, 1996Date of Patent: September 15, 1998Assignee: Thin Film Technology CorporationInventor: Mark Brooks
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Patent number: 5804004Abstract: A method for fabricating a multichip module includes attaching a first integrated circuit to a silicon circuit board. Bonding pads on the first integrated circuit are wire-bonded to a first set of contacts on the circuit board. A second integrated circuit is adhesively attached onto the top of the first integrated circuit. The second integrated circuit includes a recessed bottom surface to provide an overhang over the first integrated circuit which exposes the bonding pads on the top surface of the first integrated circuit. Then bonding pads on the second integrated circuit are wire-bonded to a second set of contacts on the circuit board.Type: GrantFiled: May 24, 1996Date of Patent: September 8, 1998Assignee: nChip, Inc.Inventors: David B. Tuckerman, Nicholas E. Brathwaite, Paul Marella, Kirk Flatow
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Patent number: 5778528Abstract: A wiring construction of an electrical connection box which has an internal circuit including a wire and a plurality of pressing contact terminals connected to the wire and in which an insulating plate is accommodated in a casing, the wiring construction comprising: a plurality of wiring grooves for receiving the wire or a plurality of pairs of wiring projections for guiding the wire therebetween, which are provided on at least one of opposite faces of the insulating plate such that predetermined portions of the wiring grooves or the wiring projections extend to an outer peripheral edge of the insulating plate; wherein a nonconnective portion of the wire is disposed at the outer peripheral edge of the insulating plate by cutting from the wire a portion of the wire projecting out of the outer peripheral edge of the insulating plate.Type: GrantFiled: October 3, 1996Date of Patent: July 14, 1998Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Yuuji Saka, Takahiro Onizuka, Yoshito Oka, Makoto Kobayashi, Nori Inoue
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Patent number: 5764486Abstract: An electrical interconnection between a flip chip and a substrate. The interconnection includes a substrate having conductive pads to which wire bumps are attached. Each wire bump includes an elastically deformable stub section attached to the ball section, and a pointed tip. The pointed tip pierces a soft conductive layer located on a conductive pads of a flip chip. The elastic deformation of the stub section provides for consistent electrical connections between the flip chip and the substrate when the flip chip and the substrate are non-planar. An adhesive is located between the flip chip and the substrate and encompasses the wire bumps.Type: GrantFiled: October 10, 1996Date of Patent: June 9, 1998Assignee: Hewlett Packard CompanyInventor: Rajendra D. Pendse
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Patent number: 5735967Abstract: A linear body disposing method capable of extending a large number of wires above a work efficiently provides a plurality of collector wires on a substrate coated with a photosensitive film. The plurality of collector wires are held at a predetermined interval therebetween before one end of the substrate. The plurality of held collector wires are drawn to the other end of the substrate simultaneously. The other end of each of said drawn collector wires is fixed on the substrate. Subsequently, while the collector wires are held at the one end of the substrate, one end of each of the collector wires is fixed to the one end of the substrate. Thereafter, the collector wires are cut.Type: GrantFiled: July 5, 1996Date of Patent: April 7, 1998Assignee: Canon Kabushiki KaishaInventors: Takeshi Yakou, Tsunenobu Satoi, Eiji Takaki, Toshio Akiyama
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Patent number: 5722161Abstract: A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a "keyhole" cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region.Type: GrantFiled: May 1, 1996Date of Patent: March 3, 1998Assignee: Amkor Electronics, Inc.Inventor: Robert C. Marrs
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Patent number: 5708419Abstract: A method of electrically connecting an integrated circuit (IC) to at least one electrical conductor on a flexible substrate. A flexible dielectric substrate has an IC attachment area and at least one resonant circuit formed thereon. The resonant circuit is formed with a first conductive pattern disposed on a first principal surface of the flexible substrate and a second conductive pattern disposed on a second, opposite principle surface of the flexible substrate. The first conductive pattern is electrically connected to the second conductive pattern such that the first and second conductive patterns form an inductor and a capacitor, with the inductor also functioning as an antenna. The IC attachment area of the flexible substrate is cleaned and the flexible substrate is secured in a fixed position in a plenum to prevent substantial movement thereof. The IC is secured to the IC attachment area of the flexible substrate to minimize movement of the IC relative to the flexible substrate.Type: GrantFiled: July 22, 1996Date of Patent: January 13, 1998Assignee: Checkpoint Systems, Inc.Inventors: Mark R. Isaacson, Anthony F. Piccoli, Michael Holloway
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Patent number: 5704115Abstract: A self-closing main distributing frame of any shape, (e.g. rectangular) which increases its capacity by growth in the vertical direction. The frame includes a stack of self-closing horizontal planes, or shelves, open to the outer face, and supported by brackets attached to vertical members on the interior face.Type: GrantFiled: May 8, 1995Date of Patent: January 6, 1998Inventor: Kenneth James Warburton
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Patent number: 5701666Abstract: A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.Type: GrantFiled: April 16, 1997Date of Patent: December 30, 1997Assignee: Motorola, Inc.Inventors: Robert Keith DeHaven, James F. Wenzel
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Patent number: 5699606Abstract: An electrical heating element for a radiant electric heater takes the form of an elongate electrically conductive strip for partial embedding edgewise in a base of thermal and electrical insulation material. The strip is composed of an elongate continuous portion and an elongate discontinuous portion integral with the continuous portion. The discontinuous portion is intended for embedding in the base and is provided with a plurality of discontinuities so that in operation of the heater current flow in the discontinuous portion is reduced or eliminated.Type: GrantFiled: November 14, 1995Date of Patent: December 23, 1997Assignee: Ceramaspeed LimitedInventor: Joseph Anthony McWilliams
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Patent number: 5697149Abstract: A technique of coating an electronic component with a resin. A semiconductor chip is placed on an insulating film carrying electric contacts to which the semiconductor chip is connected by connection wires passing through holes formed in the insulating film. The holes in the insulating film are placed around a zone for receiving the semiconductor chip, and the semiconductor chip is placed on the insulating film in such zone. The connection wires are connected between the semiconductor chip and the electric contacts, and a drop of resin is deposited on the semiconductor chip and on the connection wires. This drop forms an outline defined solely by the holes due to surface tension applied by the resin retained in the holes. This arrangement is applicable to electronic modules for memory cards.Type: GrantFiled: April 25, 1996Date of Patent: December 16, 1997Assignee: Schlumberger IndustriesInventor: Robert Munch
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Patent number: 5694680Abstract: To provide wire laying method and apparatus which realize high utilization of a wire laying space by pressing a plurality of wires one over another in a wire groove formed in an insulating plate, wires 2A to 2C drawn from a wire laying head 5 are, while being inserted into a wire groove 1a using a natural bend R, forcibly pressed to specified depths by a pressing pin 11 in synchronism with the movement of the wire laying head 5.Type: GrantFiled: August 14, 1995Date of Patent: December 9, 1997Assignee: Sumitomo Wiring Systems, Ltd.Inventors: Takayuki Yamada, Hiroshi Rokutani, Nori Inoue
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Patent number: 5649352Abstract: The process for assembly of a coil with or without a core on a printed circuit comprises placing the printed circuit in the winding machine before starting the winding. When the Flyer brings the wire for the winding, it causes the latter to pass over a metallized path of the printed circuit while keeping said wire taut. After the Flyer has effected the number of turns necessary for the winding, it will carry the wire along, passing onto a second metallized path, always keeping it taut. The soldering of the two end wires of the winding on the respective metallized paths will take place very easily since each of said wires is held taut at the location where the soldering is to take place. This process permits automating the production of miniaturized electronic circuits comprising a winding.Type: GrantFiled: March 31, 1995Date of Patent: July 22, 1997Assignee: Sokymat S.A.Inventor: Ake Gustafson
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Patent number: 5638290Abstract: A method for removing the critical false paths takes place during logic optimization. It is based on a path-constrained redundancy removal algorithm. This path-constrained redundancy removal algorithm automatically finds that a path node does not affect the behavior of the path output and so determines a critical path. This method is iteratively repeated for as long as this critical path is false.Type: GrantFiled: April 6, 1995Date of Patent: June 10, 1997Assignee: VLSI Technology, Inc.Inventors: Arnold Ginetti, Christophe Gauthron
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Patent number: 5630271Abstract: A unique general-purpose circuit board and a unique burning jig implement a wiring pattern for the trial manufacture of a new electronic circuit. The circuit board is implemented as an insulative plate on which horizontal and vertical parallel conductive lines are provided, and in which through holes are formed at the junctions of the lines. Each through hole is surrounded by four conductive portions insulated from each other and each being connected to a particular conductive line. The burning jig has a flat base and burning pins studded on the base and each corresponding to one of the through holes. Each burning pin has four metal pieces at one end thereof. The four metal pieces are insulated from each other and respectively correspond to the four conductive portions surrounding a single through hole.Type: GrantFiled: September 27, 1995Date of Patent: May 20, 1997Assignee: NEC CorporationInventor: Kei Suzuki
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Patent number: 5616524Abstract: A method of repairing an open circuit defect in a damaged address line in a thin film electronic imager device includes the steps of forming a repair area on the device so as to expose the open-circuit defect in the damaged address line and then depositing a conductive material to form a second conductive component and to coincidentally form a repair shunt in the repair area so as to electrically bridge the defect. The step of forming the repair area includes the steps of ablating dielectric material disposed over the first conductive component in the repair area, and etching the repair area so as to remove dielectric material disposed over the defect in the address line in the repair area such that the surface of the address line conductive material is exposed but is not contaminated by the removal of the overlying dielectric material.Type: GrantFiled: December 22, 1995Date of Patent: April 1, 1997Assignee: General Electric CompanyInventors: Ching Y. Wei, Jianqiang Liu, Roger S. Salisbury, Robert F. Kwasnick, George E. Possin, Douglas Albagli
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Patent number: 5584956Abstract: A method for producing feedthroughs in a substrate having a front and back surface, wherein the substrate either has a hole or absorbs radiation at a given wavelength. The method includes selecting and intimately bonding a sheet to the back surface of the substrate with an adhesive which is absorptive at the given wavelength. If the substrate has a hole, an exposed area of the sheet is illuminated with laser radiation at the given wavelength and at a power level sufficient to ablate a portion of the sheet behind the exposed area, thereby creating the feedthrough in the substrate. If the substrate has no hole, an area on the front surface of the substrate is illuminated with laser radiation at the given wavelength and at a power level sufficient to ablate a portion of the substrate and a portion of the sheet behind the area, thereby creating the feedthrough in the substrate. The sheet can then be removed from the substrate.Type: GrantFiled: May 9, 1994Date of Patent: December 17, 1996Assignee: University of Iowa Research FoundationInventors: Janet K. Lumpp, Susan D. Allen
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Patent number: 5584121Abstract: An adhesive comprising (a) solid epoxy resin having a molecular weight of 5000 or more, (b) a polyfunctional epoxy resin having at least three epoxy groups, (c) an intramolecular epoxy modified polybutadiene having at least three epoxy groups, (d) a cationic photoinitiator, and (e) a tin compound in special weight ratios, is effective for producing multiple wire wiring boards having good heat resistance, solvent resistance wherein the adhesive layer has no voids and prevents shift of insulated encapsulated wires.Type: GrantFiled: June 5, 1995Date of Patent: December 17, 1996Assignee: Hitachi Chemical Company, Ltd.Inventors: Shigeharu Arike, Yorio Iwasaki, Eiichi Shinada, Toshiro Okamura, Kanji Murakami, Yuichi Nakazato
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Patent number: 5557842Abstract: A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).Type: GrantFiled: May 30, 1995Date of Patent: September 24, 1996Assignee: Motorola, Inc.Inventor: Keith W. Bailey
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Patent number: 5542171Abstract: A method of making a transfer molded chip carrier. A semiconductor device (10) is first electrically and mechanically attached to a substrate (12). The substrate (12) is then treated by sputter etching so that it will provide good adhesion between the substrate and a molding compound (18) that is subsequently molded to the substrate (25). Portions of the treated substrate are then selectively contaminated in order to reduce the adhesion between these selected portions of the substrate and the molding compound. The molding compound is then formed around the semiconductor device so as to encapsulate it and also part of the surface of the substrate. Portions (20) of the transfer molded material that were molded over the selectively contaminated portions of the substrate (12) are then removed by breaking away.Type: GrantFiled: October 4, 1991Date of Patent: August 6, 1996Assignee: Motorola, Inc.Inventors: Frank J. Juskey, Anthony B. Suppelsa, Fadia Nounou
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Patent number: 5531022Abstract: The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough.Type: GrantFiled: September 2, 1994Date of Patent: July 2, 1996Assignee: International Business Machines CorporationInventors: Brain S. Beaman, Fuad E. Doany, Keith E. Fogel, James L. Hedrick, Jr., Paul A. Lauro, Maurice H. Norcott, John J. Ritsko, Leathen Shi, Da-Yuan Shih, George F. Walker
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Patent number: 5517747Abstract: A coaxial-to-coplanar waveguide connector is used for interconnecting stripline compatible devices utilizing coaxial cable. The connector is formed at the end of a length of coaxial cable embedded within a circuit board. The connector generally has a substantially semi-circular connection section. The connection section includes a conductor partly surrounded by an electrically insulative dielectric which is partly surrounded by a shield. An electrically conductive sheet is used to couple the shield to a ground plane of the circuit board. Electrically conductive ribbon is connect the conductor to a stripline compatible device. The coaxial-to-coplanar waveguide connector may be fabricated by coating a dielectric board with an adhesive material and then routing a length of miniature coaxial cable in the adhesive. Conductive material and dielectric material are consecutively laid upon the dielectric cable board.Type: GrantFiled: December 29, 1994Date of Patent: May 21, 1996Assignee: AIL Systems, Inc.Inventors: John A. Pierro, Thomas H. Graham, Scott M. Weiner, Paul Heller, Joseph L. Merenda
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Patent number: 5515606Abstract: Wiring of terminals of electrical apparatus or apparatus systems (4, 5, 7) is done automatically in the course of the direct wiring. A preassembled electrical apparatus or apparatus system is made available with terminals (9, 10, 11) fixedly located in it, whereupon by means of an automatically guided line-laying tool (59), an endlessly supplied line (68) is moved into the contacting zones of the specially formed terminals, fixed there, and either clipped or through-wired.Type: GrantFiled: February 3, 1994Date of Patent: May 14, 1996Assignee: Vossloh Schwabe GmbHInventors: Bernhard Albeck, Herbert Emmerich, Stefan Koller, Hans-Peter Mews
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Patent number: 5508628Abstract: A pivoting beam or lever is used to open and close burn-in and test sockets which employ laterally moving cammed plates to form electrical contact between electrical contact fingers within the socket and terminals depending from an electronic device package. The pivoting beam is oriented and adapted for operation by vertically applied forces so that opening and closing the socket is easily automatible using the pick and place equipment conventionally used to insert and remove electronic device packages from open top sockets.Type: GrantFiled: February 1, 1995Date of Patent: April 16, 1996Inventor: Wayne K. Pfaff
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Patent number: 5493076Abstract: The present invention relates generally to a new structure and a method for repairing semiconductor substrates, and more particularly, the invention encompasses a structure and a method for repairing Printed Circuit Boards or other electronic substrates by providing electrical lines on the defective board. On a substrate that has an open or an electrical discontinuity, after the discontinuity has been established, a portion of the electrical line across from the electrical discontinuity are exposed and one or more trenches or grooves are made between the two or more exposed portions of the electrical line. The two exposed portions of the exposed electrical line is then joined by either an electrical wire that is routed through the trench or using a standard deposition process one or more metals or material are deposited in the open trench to provide or restore electrical continuity and the excess deposition material is removed.Type: GrantFiled: January 26, 1995Date of Patent: February 20, 1996Assignee: International Business Machines CorporationInventors: James M. Levite, Michael Berger, Richard L. Chartrand, Mary A. Emmett, Raymond A. Jackson, James J. Petrone, Richard F. Shortt, Roger A. Stinemire
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Patent number: 5477605Abstract: A radiant electric heater having an electric heating element in the form of an elongate electrically conductive strip supported on edge and partially embedded in a layer of microporous thermal and electrical insulation material in a support dish is manufactured by placing an elongate electrically conductive strip on edge in a groove in a press tool, such that a portion of the strip protrudes from the groove, the groove being formed of a pattern corresponding to that required for a heating element in the heater. A predetermined quantity of powdery microporous thermal and electrical insulation material is arranged between the press tool and a support dish of the heater, and the insulation material is compressed into the support dish with the press tool, the material being compacted to form a layer of a desired density and simultaneously compacted against the portion of the strip protruding from the groove, to secure the strip on edge in partial embedment in the layer of the insulation material.Type: GrantFiled: May 19, 1994Date of Patent: December 26, 1995Assignee: Ceramaspeed LimitedInventors: Joseph A. McWilliams, Ali Paybarah