By Using Wire As Conductive Path Patents (Class 29/850)
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Publication number: 20100071935Abstract: A shielded flexible cable having a plurality of shielded electronic circuits in close proximity to one another such that signals transmitted on one of said plurality of shielded electronic circuits do not substantially interfere with signals transmitted on the other of said plurality of electronic circuits comprising a polyimide support member supporting a plurality of etched copper traces on a first side of said polyimide support member and a copper layer on a second side of said polyimide support member. Said polyimide support member is flexible along at least one axis, and said plurality of etched copper traces and said copper layer substantially as flexible as said polyimide support member.Type: ApplicationFiled: December 4, 2009Publication date: March 25, 2010Applicant: MULTI-FINELINE ELECTRONIX, INC.Inventors: DALE J. WESSELMAN, CHARLES E. TAPSCOTT
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Publication number: 20100071951Abstract: The multilayer wiring board is provided with a lower layer wiring (8), and an upper layer wiring (10) formed on the lower layer wiring (8) through an interlayer insulating layer (9). On the interlayer insulating layer (9), a contact hole (11) is provided for interconnecting the upper layer wiring (8) with the lower layer wiring (10). A region surrounded by an inner wall (13) which forms the contact hole (11) is permitted to have a linewidth region wherein a wide line region (13A) and protruding regions (13B, 13C) as regions having different linewidths are connected. Thus, film thickness distribution of an ink baked product (12) formed at the contact hole (11) rises at the protruding regions (13B, 13C), and highly reliable multilayer interconnection can be performed between the lower layer wiring (8) and the upper layer wiring (10).Type: ApplicationFiled: August 14, 2006Publication date: March 25, 2010Inventors: Tokuo Yoshida, Akiyoshi Fujii, Tatsuya Fujita
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Publication number: 20100068880Abstract: A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer (11) on a semiconductor substrate (2) including an element region (2b), a recess step of forming a recess (12) in the insulation layer (11), a metal layer step of embedding a metal layer (13) in the recess (12), a planarization step of planarizing a surface of the insulation layer (11) and a surface of the metal layer (13) to be substantially flush with each other, and a metal cap layer step of forming a metal cap layer (16) containing at least zirconium element and nitrogen element on the surface of the insulation layer (11) and the surface of the metal layer (13) after the planarization step.Type: ApplicationFiled: February 25, 2008Publication date: March 18, 2010Inventors: Masanobu Hatanaka, Kanako Tsumagari, Michio Ishikawa
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Publication number: 20100065320Abstract: Disclosed is a wiring board comprising a plurality of conductors (11) having a conductive member including first conductive material (1) and second conductive material (2), and insulating member (3) covering the conductive member. A plurality of conductors (11) are arranged lattice-like and are weaved like a woven cloth, and sections intersecting with each other are electrically connected.Type: ApplicationFiled: December 6, 2007Publication date: March 18, 2010Applicant: NEC CORPORATIONInventor: Wataru Urano
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Publication number: 20100064512Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.Type: ApplicationFiled: October 29, 2009Publication date: March 18, 2010Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Hironori Tanaka
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Publication number: 20100058273Abstract: An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value.Type: ApplicationFiled: June 30, 2009Publication date: March 4, 2010Applicant: Fujitsu LimitedInventor: Hideaki Katagiri
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Publication number: 20100032197Abstract: A method for fabricating a circuit board includes providing a first substrate, forming a circuit on the first substrate, the circuit having a first electrode, a second electrode and at least one nanostructure, and transferring the circuit from the first substrate to a surface of a second substrate made of a polymer.Type: ApplicationFiled: September 19, 2008Publication date: February 11, 2010Applicant: SNU R&DB FoundationInventors: Seung Hun Hong, Sung Myung, Ju Wan Kang
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Patent number: 7645941Abstract: A shielded flexible cable having a plurality of shielded electronic circuits in close proximity to one another such that signals transmitted on one of said plurality of shielded electronic circuits do not substantially interfere with signals transmitted on the other of said plurality of electronic circuits comprising a polyimide support member supporting a plurality of etched copper traces on a first side of said polyimide support member and a copper layer on a second side of said polyimide support member; said polyimide support member flexible along at least one axis; said plurality of etched copper traces and said copper layer substantially as flexible as said polyimide support member; a silver based material, including, for example, silver ink or silver film, surrounding a portion of each of said plurality of copper traces along substantially the entire length of each of said plurality of copper traces; said silver based material in electrical communication with (i) said copper layer via discontinuities inType: GrantFiled: April 24, 2007Date of Patent: January 12, 2010Assignee: Multi-Fineline Electronix, Inc.Inventors: Dale J. Wesselman, Charles E. Tapscott
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Patent number: 7643311Abstract: An electronic device protected against electromagnetic disturbances comprising: a support structure having a first and second electronic component, wherein the support structure includes a conductive means surrounding each of the first and second electronic components; a first and second insulating block formed overlying the first and second electronic components on the support structure; and a metal layer overlying the first and second insulating blocks that are formed over the first and second electronic components, wherein the metal layer is electrically connected to the support structure through the conductive means to protect the first and second electronic components from the electromagnetic disturbances irradiating from each of the first and second electronic components.Type: GrantFiled: April 20, 2006Date of Patent: January 5, 2010Assignee: STMicroelectronics SAInventor: Romain Coffy
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Patent number: 7640660Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).Type: GrantFiled: April 19, 2007Date of Patent: January 5, 2010Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani
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Publication number: 20090321124Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.Type: ApplicationFiled: June 23, 2009Publication date: December 31, 2009Inventors: Yutaka KUMANO, Hideki IWAKI, Tetsuyoshi OGURA, Shingo KOMATSU, Koichi HIRANO
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Publication number: 20090321953Abstract: A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit.Type: ApplicationFiled: September 9, 2008Publication date: December 31, 2009Inventor: Tae Min KANG
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Publication number: 20090266584Abstract: It is an object to improve a conventional point that mounting an electronic component that requires a high current and heat radiation, such as an LED, together with other general electronic components on the same board has been difficult. To achieve this object, a different thickness lead frame partially having different thicknesses is used. On a thick portion of the different thickness lead frame, a special electronic component, such as an LED, for which a high current and heat radiation are required is mounted. Further, a thin portion of the different thickness lead frame is formed at a fine pitch, and general electronic components are mounted at a high density on the thin portion. Thus, unitization or modularization of electronic components for which a high current and heat radiation are required becomes possible.Type: ApplicationFiled: September 25, 2006Publication date: October 29, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tetsuya Tsumura, Hiroharu Nishiyama, Etsuo Tsujimoto
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Publication number: 20090260867Abstract: A printed circuit board substrate includes a metal-clad substrate and a number of N spaced circuit substrates arranged on the metal-clad substrate along an imaginary circle, N is a natural number greater than 2. The circuit substrates are equiangularly arranged about the center of the circle, and each of the circuit substrates is oriented 360/N degrees with respect to a neighboring printed circuit board.Type: ApplicationFiled: December 10, 2008Publication date: October 22, 2009Applicant: FOXCONN ADVANCED TECHNOLOGY INC.Inventors: PAI-HUNG HUANG, CHIH-KANG YANG, CHENG-HSIEN LIN
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Publication number: 20090212430Abstract: Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (120, 135) is associated with another material (130, 125) such as a metal. The carbon nanotube material facilitates the electrical connection between different circuit components.Type: ApplicationFiled: November 4, 2005Publication date: August 27, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventor: Christopher Wyland
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Publication number: 20090195998Abstract: A mounting region having a rectangular shape is provided at an approximately center of one surface of an insulating layer. A plurality of conductive traces are formed so as to outwardly extend from the inside of the mounting region. A cover insulating layer is formed so as to cover the plurality of conductive traces in a periphery of the mounting region. An electronic component is mounted on the insulating layer so as to overlap with the mounting region. A metal layer is provided on the other surface of the insulating layer. Openings having a rectangular shape are formed in the metal layer along a pair of longer sides and a pair of shorter sides of the mounting region. The openings are opposite to part of terminals of the plurality of conductive traces, respectively, with the insulating layer sandwiched therebetween.Type: ApplicationFiled: January 22, 2009Publication date: August 6, 2009Applicant: NITTO DENKO CORPORATIONInventors: Yasuto ISHIMARU, Hirofumi EBE
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Publication number: 20090195997Abstract: A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in the periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A slit is formed in the metal layer so as to cross a region being opposite to the electronic component and to divide the metal layer.Type: ApplicationFiled: January 20, 2009Publication date: August 6, 2009Applicant: NITTO DENKO CORPORATIONInventors: Yasuto Ishimaru, Hirofumi Ebe
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Publication number: 20090184726Abstract: Provided is a probe card and method of fabricating the same. This method comprises forming soldering bumpers electrically connected to conductive patterns on a substrate, forming probes connected to the conductive patterns and supported by the soldering bumpers, and then melting the soldering bumpers to fixing the probes to the substrate. Forming the soldering bumpers includes a step of forming the soldering bumpers in the same pattern and size by means of a photolithography process.Type: ApplicationFiled: October 19, 2006Publication date: July 23, 2009Inventors: Oug-Ki Lee, Kyu-Hyun Shin, Seong-Hoon Jeong
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Publication number: 20090173529Abstract: A circuit structure and a fabrication method thereof manly use a plurality of wires to connect in series a plurality of pads to form a stretchable circuit. Each of the wires has a first end, a second end and an intermediate segment located between the first end and the second end, wherein the first end and the second end are respectively connected to different pads, and the position of the intermediate segment is higher than the positions of the first end and the second end. Since the connection manner of the wires and the pads has 3-D freedoms, the circuit structure can withstand both horizontal and vertical deformations and has an outstanding reliability.Type: ApplicationFiled: August 11, 2008Publication date: July 9, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Chang Lee, Yu-Hua Chen, Ying-Ching Shih, Cheng-Ta Ko
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Publication number: 20090113704Abstract: A producing method of a wired circuit board includes the steps of preparing an insulating base layer, forming a wire on the insulating base layer, forming an insulating cover layer on the insulating base layer so as to cover the wire, and irradiating the insulating cover layer with light with a wavelength of more than 700 nm and less than 950 nm to inspect for foreign substance with a reflected light from the insulating cover layer.Type: ApplicationFiled: October 9, 2008Publication date: May 7, 2009Applicant: Nitto Denko CorporationInventor: Yoshihiro Toyoda
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Patent number: 7516544Abstract: In one aspect of the invention is a method for reducing crosstalk and maintaining clearances between traces on a printed circuit board design. Crosstalk caused by placing traces a virtual printed circuit board are reduced by placing artificial obstructs, called spacers, between traces and/or between traces and nets to create a user-specified clearance between the traces and/or nets. As additional traces and/or nets are added to the virtual printed circuit board, the spacers are dynamic and adjust accordingly to maintain the specified clearances.Type: GrantFiled: June 22, 2001Date of Patent: April 14, 2009Assignee: Mentor Graphics CorporationInventor: Vladimir V. Petunin
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Publication number: 20090090004Abstract: A method for manufacturing a printed circuit board having a substrate composed of an insulation material, a via hole formed in the substrate, and a via land formed around the opening of the via hole on a surface of the substrate includes processes of measuring deformation of the substrate having the via hole formed therein, calculating a position where the via land is to be patterned on the basis of the deformation of the substrate measured in the measurement process, and patterning the via land at a position corrected on the basis of the value calculated in the calculation process.Type: ApplicationFiled: October 23, 2008Publication date: April 9, 2009Applicant: ALPS ELECTRIC CO., LTD.Inventor: Hiroshi KUBOTA
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Publication number: 20090072651Abstract: The present invention relates to a slotless winding for a rotating electric machine and a manufacturing method thereof. The slotless winding includes at least one flexible printed circuit board having at least one circuit, and one piece of flexible printed circuit board(s) is curved or a plurality of pieces of flexible printed circuit board(s) is mutually combined to form a barrel shape, thereby simplifying the procedure of manufacturing the slotless winding, improving production speed and reliability, and enabling diversified designing schemes to meet the demands of the rotating electric machine. In addition, it is not necessary for the coil winding to be cured for assembling, and assembling yield is thus enhanced.Type: ApplicationFiled: December 19, 2007Publication date: March 19, 2009Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTREInventors: Guo-Jhih YAN, Guang-Miao HUANG, Hsin-Te WANG, Liang-Yi HSU, Mi-Ching TSAI
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Publication number: 20090052029Abstract: Optical films formed by deposition of highly oriented nanowires and methods of aligning suspended nanowires in a desired direction by flow-induced shear force are described.Type: ApplicationFiled: October 12, 2007Publication date: February 26, 2009Applicant: CAMBRIOS TECHNOLOGIES CORPORATIONInventors: Haixia Dai, Manfred Heidecker, Benny Chun Hei Ng, Hash Pakbaz, Michael Paukshto, Michael A. Spaid, Cheng-I Wang
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Publication number: 20090046436Abstract: A MEMS package includes a first board, a second board and a laminate material. The first board includes a lower metallic trace, a metallic diaphragm and a through opening. The lower metallic trace is located on the lower surface of the first board, and the metallic diaphragm is disposed on the lower metallic trace. The second board includes an upper metallic trace and a metallic electrode. The upper metallic trace is located on the upper surface of the second board, the metallic electrode is disposed on the upper metallic trace, and the metallic electrode is corresponding to the metallic diaphragm. The laminate material is disposed between the lower and upper metallic traces, and includes a hollow portion for accommodating the metallic electrode and metallic diaphragm, wherein a sensing unit is formed by the metallic electrode, the hollow portion and the metallic diaphragm, and is corresponding to the through opening.Type: ApplicationFiled: May 23, 2008Publication date: February 19, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERINGInventors: Hsueh An YANG, Meng Jen WANG, Wei Chung WANG, Ming Chiang LEE, Wei Pin HUANG, Feng Chen CHENG
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Publication number: 20090038149Abstract: A method of forming at least a portion of a cable comprises providing at least one conductor, extruding at least an inner layer of polymeric insulation over the at least one conductor to form a cable conductor core, embedding a plurality of conductors into the inner layer of the cable conductor core, and extruding an outer layer of polymeric insulation over the cable conductor core and the plurality of conductors and bonding the inner layer to the outer layer to form the cable and provide a contiguous bond between the inner layer, the conductors, and the outer layer, wherein embedding comprises heating a one of the inner layer and the conductors prior to embedding the conductors into the inner layer.Type: ApplicationFiled: July 31, 2008Publication date: February 12, 2009Inventor: Joseph Varkey
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Patent number: 7480988Abstract: A method and apparatus suitable for forming hermetic electrical feedthroughs in a ceramic sheet having a thickness of ?40 mils. More particularly, the method yields an apparatus including a hermetic electrical feedthrough which is both biocompatible and electrochemically stable and suitable for implantation in a patient's body. The method involves: (a) providing an unfired, ceramic sheet having a thickness of ?40 mils and preferably comprising >99% aluminum oxide; (b) forming multiple blind holes in said sheet; (c) inserting solid wires, preferably of platinum, in said holes; (d) firing the assembly of sheet and wires to a temperature sufficient to sinter the sheet material but insufficient to melt the wires; and (e) removing sufficient material from the sheet lower surface so that the lower ends of said wires are flush with the finished sheet lower surface.Type: GrantFiled: March 30, 2001Date of Patent: January 27, 2009Assignee: Second Sight Medical Products, Inc.Inventors: Jerry Ok, Robert J. Greenberg
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Publication number: 20080314626Abstract: A sheet in an electronic display is composed of a substrate containing an array of wire electrodes. The wire electrodes are preferably electrically connected to patterned transparent conductive electrode lines. The wire electrodes are used to carry the bulk of the current. The wire electrodes are capable of being extended away from the substrate and connected directly to the printed circuit board. The transparent conductive electrode (TCE) is used to spread the charge or voltage from the wire electrode across the pixel. The TCE is a patterned film and must be at least 50% transparent, and, for most applications, is preferably over 90% transparent. In most applications, the electroded surface of the electroded sheet has to be flattened. Use of a thin polymer substrate yields a light, flexible, rugged sheet that may be curved, bent or rolled.Type: ApplicationFiled: August 20, 2008Publication date: December 25, 2008Inventor: Chad B. Moore
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Publication number: 20080291655Abstract: Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device.Type: ApplicationFiled: May 21, 2008Publication date: November 27, 2008Inventors: Ji-Yong Park, Kyoung-Sei Choi
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Publication number: 20080271309Abstract: A method and apparatus for forming a substrate support is provided herein. In one embodiment, the substrate support includes a body having a support surface and at least one groove. A heater element clad with a malleable heat sink is disposed in the groove. Substantially no air is trapped between the clad heater element and the groove. An insert is disposed in the groove above the heater. The insert substantially completely covers and contacts the clad heater element and the sides of the groove. A cap is disposed in the groove above the insert. The cap covers and contacts the insert and has an upper surface disposed substantially flush with the support surface.Type: ApplicationFiled: July 23, 2008Publication date: November 6, 2008Inventors: Rolf A. Guenther, Curtis B. Hammill
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Publication number: 20080250632Abstract: A method and system for providing a conformable cable are described. The method and system may include disposing a conformable material along at least a portion of a cable and configuring the cable into a desired position and shape in which the shape of the cord remains unchanged.Type: ApplicationFiled: February 12, 2008Publication date: October 16, 2008Inventors: Douglas C. Dayton, Sung Park, Samuel L. Palmer, Elizabeth Johansen
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Publication number: 20080239684Abstract: A wiring board including, on a resin insulating layer, an Ni—Cu alloy bonding seed layer constituted by 20 to 75 wt % of Ni and Cu to be a residual part and a wiring layer constituted by Cu formed thereon is provided. It is possible to manufacture the wiring board by (A) forming the Ni—Cu alloy bonding seed layer through a one-time treatment and removing an unnecessary portion through one-time etching after wiring patterning, or (B) forming the Ni—Cu alloy bonding seed layer and a Cu layer thereon and patterning thereof in a lump by etching. A wiring board in which a wiring layer is formed by an Ni—Cu alloy constituted by 20 to 75 wt % of Ni and Cu to be a residual part over a whole thickness of the wiring layer is also provided.Type: ApplicationFiled: March 31, 2008Publication date: October 2, 2008Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Tomoo Yamasaki
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Publication number: 20080222886Abstract: A carrier substrate and a method for manufacturing the carrier substrate are disclosed herein. The method includes the steps of: providing a core substrate; forming a build-up material layer on the core substrate; forming a via in the build-up material layer; forming a patterned photoresist layer on the build-up material layer covering a portion of the via and exposing an opening from uncovered portion of the via, and a wiring slot connected to the opening; and forming a metal-electroplated layer on the via and the wiring slot. In forming a trace according to the present invention, the metal-electroplated layer is formed as the trace and directly connected to the via, striding or not striding over the via. Additionally, in the carrier substrate structure, there is no need an annular ring to connect the trace to the via, and thus the wiring space is increased.Type: ApplicationFiled: March 13, 2007Publication date: September 18, 2008Inventors: Jun-Chung Hsu, Bing-Kuen Lin, Chao-Lung Wang
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Publication number: 20080210461Abstract: A method of fabricating a circuit board includes the steps of: (a) defining a first jumper symbol and a second jumper symbol of a schematic circuit symbol library; (b) drawing the first jumper symbol and the second jumper symbol of the schematic circuit symbol library in a schematic circuit diagram for forming a three-terminal jumper symbol; (c) defining a first jumper pattern and a second jumper pattern of a PCB component pattern library; (d) calling the PCB component pattern library for drawing the first jumper pattern and the second jumper pattern in a PCB layout so as to define a three-terminal jumper pattern; (e) selecting a jumper symbol between the first jumper symbol and the second jumper symbol; and (f) mounting a jumper on the first jumper pattern or the second jumper pattern on the circuit board according to the PCB layout and a select result from step (e).Type: ApplicationFiled: July 5, 2007Publication date: September 4, 2008Inventors: Chien-Hung Chen, Shu-Chih Chen
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Publication number: 20080190652Abstract: A wired circuit board includes: a first insulating layer; a conductive pattern formed on the first insulating layer and having a terminal portion; and a second insulating layer formed on the first insulating layer to cover the conductive pattern. A surface of the terminal portion is formed to be exposed from the first insulating layer and the second insulating layer. A tin alloy layer is formed at least on a top surface and both side surfaces of the terminal portion.Type: ApplicationFiled: February 8, 2008Publication date: August 14, 2008Applicant: Nitto Denko CorporationInventors: Katsutoshi Kamei, Kazuya Nakamura, Visit Thaveeprungsriporn
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Publication number: 20080185177Abstract: The invention provides a circuit board structure for electrical testing and a fabrication method thereof.Type: ApplicationFiled: March 10, 2008Publication date: August 7, 2008Applicant: PHOENIX PRECISION TECHNOLOGY CORPORATIONInventor: Pao-Hung Chou
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Patent number: 7404250Abstract: A method of fabricating a printed circuit board having a coaxial via, includes. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.Type: GrantFiled: December 2, 2005Date of Patent: July 29, 2008Assignee: Cisco Technology, Inc.Inventors: Wheling Cheng, Roger Karam, Sergio Camerlo
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Publication number: 20080144300Abstract: The present invention provides a circuit board in which generation of a white-blushed mark which is partially produced at a blank portion having no wiring pattern at a rim of an opening portion is suppressed when forming the opening portion by punching, and a manufacturing method thereof in the circuit board in which a portion where a wiring pattern is dense and the blank portion having no wiring pattern are present at a rim of a central part of the circuit board. There is provided a circuit board having an opening portion formed at the center of the circuit board by punching, the circuit board having a structure where a dummy electrode pattern connected with a rim of the opening portion is provided besides a wiring pattern which is connected with the opening portion at the rim of the opening portion and used for wire bonding. It is preferable to provide the dummy electrode pattern having a size satisfying S/d?0.Type: ApplicationFiled: December 14, 2007Publication date: June 19, 2008Inventor: Kiyotake Nohara
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Patent number: 7377033Abstract: A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.Type: GrantFiled: December 20, 2006Date of Patent: May 27, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 7370406Abstract: A thin film magnetic head is described, the magnetic head having an insulating layer and a protrusion which has an upper portion and a base portion, and the upper portion has an extended portion. The insulating layer is present under the extending part. A method of manufacturing the magnetic head includes forming a first insulating layer around the lower core layer; simultaneously forming a coil layer by plating the lower core layer with a coil insulating underlayer interposed between the lower coil layer and a coil lead layer connected to the coil layer on the first insulating layer; forming a coil insulating layer of an inorganic material on the coil layer and the coil lead layer; and, simultaneously forming a first plating underlayer for forming an upper core layer by plating, a second plating underlayer on the first coil lead layer exposed through the plating-forming opening, and a current-carrying lead layer.Type: GrantFiled: June 2, 2004Date of Patent: May 13, 2008Assignee: TDK CorporationInventor: Hisayuki Yazawa
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Publication number: 20080086877Abstract: A manufacturing method for imprinting stamper is disclosed. The manufacturing method includes forming a plurality of concave patterns on an insulation layer, forming a stamper by filling copper in the concave patterns, separating the stamper from the insulation layer, providing roughness on the surface of the stamper, can separate the stamper from the insulation layer, can prevent the deformation of the stamper and can manufacture pluralities of stampers repeatedly.Type: ApplicationFiled: October 10, 2007Publication date: April 17, 2008Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jeong-Bok Kwak, Seung-Hyun Ra, Choon-Keun Lee, Jae-Choon Cho, Sang-Moon Lee
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Patent number: 7353597Abstract: A method of forming a conductive gasket material by layering at least one conductive web layer having a blended mixture of conductive fibers and low melting point nonconductive fibers onto a foam core, and needlepunching the conductive web layer and the foam core forming a conductive composite gasket material having a plurality of conductive fibers interspersed through the foam core.Type: GrantFiled: January 6, 2006Date of Patent: April 8, 2008Inventor: Joseph J. Kaplo
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Patent number: 7353600Abstract: A circuit board fabrication method including: forming first conductive interconnection 2 onto insulator substrate 1; applying resin film 41, which is to be interlevel insulator layer 42 for electrically insulating first conductive interconnection 2 and second conductive interconnection 6, onto insulator substrate 1; either making pillar-like member 3 stand on a prescribed position on first conductive interconnection 2 before applying resin film 41, or press fitting pillar-like member 3 into resin film 41 so as to reach either a surface vicinity of first conductive interconnection 2 or a portion of first conductive interconnection 2 after applying resin film 41; hardening resin film 41 to form interlevel insulator layer 42; pulling out pillar-like member 3 to form opening 5 in interlevel insulator layer 42; and forming second conductive interconnection 6 onto interlevel insulator layer 42 to include opening 5.Type: GrantFiled: September 15, 2004Date of Patent: April 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Norihito Tsukahara, Kazuhiro Nishikawa, Daisuke Sakurai
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Publication number: 20080054491Abstract: A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate.Type: ApplicationFiled: September 6, 2007Publication date: March 6, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Eiichi Makino, Shigeo Ohshima, Naohisa Okumura
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Patent number: 7307020Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.Type: GrantFiled: December 18, 2003Date of Patent: December 11, 2007Assignee: Elm Technology CorporationInventor: Glenn J Leedy
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Patent number: 7302756Abstract: A wire-bonding substrate includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the in the wire-bonding substrate. A package includes a die that is coupled to the first wire-bonding pad. The package can include a larger substrate that is coupled to the wire-bonding substrate through an electrical connection such as a solder ball. A process of forming the wire-bonding substrate includes via formation to stop on the wire-bond pad. A method of assembling a microelectronic package includes coupling the die to the wire-bond pad. A computing system includes the wire-bonding substrate.Type: GrantFiled: June 30, 2003Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Brian Taggart, Ronald L. Spreitzer, Robert Nickerson
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Patent number: 7266877Abstract: The invention relates to tooling for preparing a large-section harness comprising at least one cable. The tooling includes an output module (19) for receiving the terminal end of the cable. The output module (19) comprises three tools mounted on an output body (20) that is movable on a tray (1) so that each of the tools can be presented in alternation in register with the terminal end of the cable, the tools comprising a first tool (22) for marking cutting and stripping lengths for the cable, a second tool (28) for marking the position and the orientation of the terminal connection member (29), and a third tool (30) for checking that the terminal connection member (29) is in the proper position and orientation after it has been crimped to the terminal end of the cable.Type: GrantFiled: April 3, 2006Date of Patent: September 11, 2007Assignee: EurocopterInventor: Serge Pittau
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Patent number: 7257884Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.Type: GrantFiled: August 24, 2005Date of Patent: August 21, 2007Assignee: Micron Technology, Inc.Inventors: Aaron M. Schoenfeld, David J. Corisis, Tyler J. Gomm
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Patent number: 7257883Abstract: In the manufacture of an electric heater, means (24, 26) is provided for feeding and guiding a ribbon heating element (14) progressively into overlying edgewise relationship with a base (2). Means (6, 8) is provided for supporting the base (2) and for effecting relative motion between the base (2) and the feeding and guiding means (24, 26), such that motion of the base (2) is synchronised with feeding of the element (14) as it is fed and guided into the relationship with the base (2), to urge the heating element (14) towards the base (2) and cause an edge portion (22) of the heating element (14) to become embedded in the base (2).Type: GrantFiled: January 27, 2003Date of Patent: August 21, 2007Assignee: Ceramaspeed LimitedInventor: Kevin Ronald McWilliams
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Patent number: 7243424Abstract: An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.Type: GrantFiled: February 17, 2005Date of Patent: July 17, 2007Assignee: TDK CorporationInventors: Kiyoshi Hatanaka, Haruo Nishino, Hideaki Ninomiya