Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.

Abstract: A current sense circuit includes a power transistor, a first level shifter, an operational transconductance amplifier (OTA), a second level shifter, and a dummy transistor. The power transistor has a first terminal and a power control terminal coupled to a control voltage. The first level shifter is coupled to the first terminal and pulls up a voltage of the first terminal to an operating voltage. The OTA is coupled to the first level shifter and converts the operating voltage into an operating current. The second level shifter is coupled to the OTA and pulls down the operating voltage to the voltage of the first terminal. The dummy transistor has a dummy control terminal with the control voltage, and a third terminal coupled to the second level shifter and having the same voltage as the voltage of the first terminal.

Abstract: A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.

Abstract: An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current, while the startup circuit receives the startup current and outputs an output voltage. The startup circuit includes a current mirror, a first NMOS transistor, a second NMOS transistor, diodes, and a third NMOS transistor, and a control circuit. The first and second NMOS transistors are coupled to the current mirror at their sources and are coupled to one another and to the reference circuit at their gates. The diodes are coupled between the gate of the second NMOS transistor and the source of the second NMOS transistor, and the third NMOS transistor is coupled to the source of the second NMOS transistor at its gate (which also provides the output voltage at its source). The control circuit is then coupled to the drains of the first and second NMOS transistors.

Abstract: A voltage converter to convert a high voltage to a low voltage is provided. The voltage converter comprises: a current mirror, a current bias, a plurality of loads and a low voltage output. The current mirror comprises a first PMOS and a second PMOS, wherein the source of the first PMOS and the second PMOS receive a high voltage input which is a supply voltage of the current mirror, and the gate of the first PMOS is connected to the drain of the first PMOS. The current bias is connected between the drain of the first PMOS and a ground potential. The plurality of loads are parallel connected between the drain of the second PMOS and the ground potential. And the low voltage output connected to the drain of the second PMOS.

Abstract: An impedance transformation circuit utilizes two transistor circuits.

Abstract: A chopper stabilized bandgap voltage reference circuit comprises current mirror circuitry mirroring first and second currents into first and second networks to generate a forward diode voltage signal and a PTAT (proportional to absolute temperature) component signal, and a third current having a derived temperature coefficient into a third network to generate a reference voltage signal for a regulator. An amplifier amplifies a differential signal of the forward diode voltage signal and the PTAT component signal to output a fourth current to control the first and second currents. According to a chopper clock, a modulator modulates the differential signal to be supplied to the amplifier and a demodulator demodulates the fourth current. A gain loop compensation circuit is coupled to the demodulator to compensate the amplifier, and filter the fourth current for noise components, and a bypass circuit is also provided to the third network for filtering the third current.

Abstract: Methods and apparatus are described that develop a reference voltage that is based on a difference between a threshold voltage of a first transistor and a threshold voltage of a second transistor, and further based on a difference between a gate overdrive voltage of the first transistor and a gate overdrive voltage of the second transistor.

Abstract: A reference circuit includes a first transistor having a first current electrode, a control electrode, and a second current electrode coupled to a power supply terminal. The reference circuit further includes a resistive element including a first terminal coupled to the control electrode of the first transistor and a second terminal coupled to the first current electrode. Additionally, the reference circuit includes a second transistor including a first current electrode coupled to the second terminal of the resistive element, a control electrode coupled to the second terminal, and a second current electrode coupled to the power supply terminal. The second transistor is configured to produce an output signal related to a voltage at the control electrode of the first transistor.

Abstract: There is provided a power control system. A power control system may include: a power regulator having a plurality of power PMOS transistors connected to a power source in parallel with each other; a current sensing unit connected to the power source and sensing currents flowing through a plurality of target PMOS transistors located at predetermined positions; a current mirror unit connected to a first regulated voltage terminal and generating a plurality of currents equal to the currents sensed by the current sensing unit; a comparator unit totaling the plurality of currents generated by the current mirror unit to convert the totaled currents into a voltage, and generating a voltage difference between the voltage and a predetermined reference voltage; and a current bias circuit unit controlling a bias current according to the voltage difference from the comparator unit. There is provided a power amplification system including the power control system.

Abstract: A circuit includes a first current path comprising a first floating-gate transistor having a programmable threshold voltage, a second current path, and a differential amplifier. The second current path includes a second floating-gate transistor having a programmable threshold voltage and a resistor. The differential amplifier includes a first input coupled to the first current path, a second input coupled to the second current path, and an output configured to control a reference current path.

Abstract: Provided is a band gap reference voltage circuit having an improved power supply rejection ratio. Owing to a voltage supply circuit (51), a power supply voltage (V5) does not depend on variation of a power supply voltage (Vdd). A voltage (V3?V2) which is generated across a resistor (41) and has a positive temperature coefficient is determined based not on the power supply voltage (Vdd) but on the power supply voltage (V5), and hence the voltage (V3?V2) does not depend on the variation of the power supply voltage (Vdd). As a result, the power supply rejection ratio of the band gap reference voltage circuit is improved.

Abstract: Disclosed are a circuit and a method for adaptively biasing a voltage regulator with minimal output overshoot. The circuit includes an adaptive bias current mirror circuit further including a first transistor and a second transistor, the first transistor and the second transistor having source nodes coupled to a drain node of the first transistor. The circuit includes a common node coupled to the source node of the first transistor and the source node of the second transistor, wherein a source degenerate resistor is coupled to the adaptive bias current mirror circuit and is coupled to the common node and wherein the source degenerate resistor is configured to limit an output peak current of the voltage regulator circuit.

Abstract: A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.

Abstract: A current sensing circuit for sensing the current provided to LEDs by a constant current power source includes a resistive shunt in series with the load and a current mirror having a first leg connected to a first terminal of the resistive shunt and a second leg connected to a second terminal of the resistive shunt. Both legs of the current mirror are also connected to ground. The first leg provides a reference signal to the second leg, and the second leg uses the reference signal and a voltage at the second terminal of the resistive shunt to provide a ground referenced output signal indicative of the current provided to the LEDs.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: The present invention discloses a soft-start circuit having a reference signal generator, a first current generator, a second current generator, and a soft-start capacitor. The reference signal generator generates a first signal and a second signal. The first current generator generates a first current according to the first signal, and the second current generator generates a second current according to the second signal. The soft-start capacitor is coupled to the first current generator and the second current generator, and charged by a current difference of the first current and the second current to generate a soft-start signal.

Abstract: A reference buffer circuit provides a reference voltage at an output node and comprises a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising a third MOS transistor. A positive input terminal of the amplifier receives an input voltage. A gate of the first MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to a negative input terminal of the amplifier. A gate of the second MOS transistor is coupled to the drain of the first MOS transistor, a source is coupled to a first voltage source, and a drain is coupled to the source of the first MOS transistor. A gate of the third MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to the output node.

Abstract: Provided is a constant current circuit capable of low current consumption operation, which is prevented from repeating a start-up state and a zero steady state and entering an oscillating state when power is activated. When power is activated, until a node (A) reaches a start-up state, an excitation current is continued to be supplied to a node (B), to thereby reliably start up the constant current circuit in a short period of time without repeating the start-up state and the zero steady state.

Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Abstract: A circuit having a substrate, a generator with a field effect transistor (FET) portion and a heterojunction bipolar transistor (HBT) portion integrated in the substrate, a voltage-to-voltage conveyor integrated in the substrate, a bias circuit, and a power amplifier is disclosed.

Abstract: A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor.

Abstract: An electronic device is provided comprising a driver for light emitting semiconductor devices. The driver includes a first MOS transistor (MN1) coupled with a channel to the light emitting semiconductor device at an output node. The first MOS transistor (MN1) is configured to determine a current through the light emitting semiconductor device (LED). A control loop is provided so as to control the first MOS transistor to maintain the magnitude of the current through the light emitting semiconductor device at a target value when a voltage drop across the first MOS transistor (MN1) changes. A second MOS transistor is coupled to the output node and biased so as to supply an auxiliary current to the output node, when the voltage drop across the first MOS transistor drops below a minimum voltage level and a feedback loop is provided to reduce the current through the light emitting semiconductor device by an amount proportional to the auxiliary current.

Abstract: In a conventional bias circuit, as a power supply voltage increases, a current supplied to a bandgap reference becomes unstable due to a fluctuation of the power supply voltage, which makes it impossible for the bias circuit to perform stable bias operations in some cases. A bias circuit of the present invention has a bandgap reference, and includes a first current path supplying a drive current to the bandgap reference, and a second current path supplying a current to the bandgap reference for a predetermined period of time after power-on.

Abstract: A power supply circuit includes an output driver transistor, a buffer circuit, and an error amplification circuit. The buffer circuit includes a first transistor connected to an output terminal and a second transistor functioning as a load for the first transistor. The error amplification circuit includes a differential pair including a first pair of transistors, a current mirror circuit including a second pair of transistors, a constant current source supplying a current and driving the differential pair and the current mirror circuit, a third transistor connected between one of the differential pair and the current mirror circuit. The first and second transistor have the same polarity as the transistors constituting the current mirror circuit, and control terminals of the first and third transistors are connected at a first junction node that is connected to a second junction node between the one of the differential pair and the third transistor.

Abstract: In a cascode current-mirror circuit which reproduces a reference current generated by a current source and outputs the reproduced reference current: the control electrodes of first and second transistors are connected; a third transistor is cascode-connected to the first transistor through a current electrode; a fourth transistor is cascode-connected to the second transistor; the control electrodes of the third and fourth transistors are connected; the control electrode of a fifth transistor is connected to the control electrode of the first transistor and another current electrode of the third transistor, and is to be connected to the current source; and a bias-voltage generation circuit generates bias voltages for the third and fourth transistors on the basis of voltages of the control electrodes of the first and the fifth transistors.

Abstract: A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.

Abstract: In a traditional, fully-isolated bandgap reference circuits, it was difficult to detect currents that are proportional to absolute temperature (PTAT). Here, a PTAT reference in a fully isolated NPN-based bandgap references are disclosed. These circuits in particular are able to make detections using various current without the need for stand-along operational amplifiers.

Abstract: A differential amplifier circuit receives a pair of input signals to develop an output signal. First and second MOS transistors have commonly-connected gates and sources. A third MOS transistor has a drain connected to the commonly-connected gates, and a source connected to the first MOS transistor's drain. The third MOS transistor's gate is connected to a constant voltage source. A constant current source is connected to the third MOS transistor's drain. A first terminal, connected to the first MOS transistor's drain and to the third MOS transistor's source, provides an input current. A second terminal, connected to the first and second MOS transistors' commonly-connected sources, provides a common reference. A third terminal, connected to the second MOS transistor's drain, provides an output current.

Abstract: In a constant current circuit that supplies a constant current Ic to a circuit connected to a current output terminal, the first transistor M1 is disposed on a current path of the constant current Ic. The second transistor and the first transistor have commonly connected gate terminals which are control terminals. The first current-voltage converting unit converts the current Im2 flowing through the second transistor into a voltage. A constant current source generates a reference current Iref. The second current-voltage converting unit converts the reference current into a voltage. Into the first error amplifier, voltages Vx1, Vx2 are input, so as to adjust the gate voltage of the first and second transistors. A voltage adjusting unit adjusts the voltage at the gate terminal of the third transistor so that the voltage at one end of the second transistor will be approximated to a predetermined reference voltage.

Abstract: A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path connected in series with a resistor between the power supply voltage and ground. This startup current is conducted via a diode-connected MOS transistor in a first leg of a current mirror. Temperature compensation is maintained by a reference leg in the current mirror that includes a bipolar transistor having an emitter area N times larger than that of a bipolar transistor in a second leg of the current mirror, to establish a temperature-compensated current in the reference leg. A compensation capacitor connected between the collector and base of a bipolar transistor in the first leg suppresses oscillation, and can be modest in size due to the Miller effect.

Abstract: A high linearity voltage-current converter able to compensate for mobility degradation comprises a first constant current source circuit, a first current mirror unit, a second constant current source circuit, a second current mirror unit, a seventh MOS transistor and an eighth MOS transistor. The first current mirror unit is coupled to the first constant current source circuit, and the second current mirror unit is coupled to the second constant current source circuit. The seventh MOS transistor, the first current mirror unit and the second current mirror unit are coupled to each other at a third joint point of a first conducting wire. The eighth MOS transistor is coupled to the seventh MOS transistor. Thereby, the electronic components used in the present invention can operate more efficiently.

Abstract: A control circuit U1 comprises four PMOS transistors MP1-MP4 and receives a voltage Vn and a voltage Vss. MP1 and MP3, and, MP2 and MP4 are respectively connected in series between power supply Vdd and a fixed voltage Vss. Gate terminal of MP2 is connected to Vss. Reference current and its copy current F1 respectively flow through NMOS transistors M1 and M2, of which respective source terminals are connected to Vss. Gate width of M2 is a quarter of that of M1. Drain terminal is connected to the gate terminals of MP1 and MP2. Node between source terminal of MP2 and drain terminal of MP3 is connected to gate terminal of MP1, and node between source terminal of MP2 and drain terminal of MP4 is connected to gate terminal of MP2. The control circuit U1 controls gate terminal voltage of M1 to make an overdrive voltage of M1 becomes Vn.

Abstract: In order to prevent interference of signals in a plurality of outputs from a current mirror circuit, the current mirror circuit comprises a current mirror input transistor Q1 through which a constant current flows and a plurality of current mirror output transistors Q7 and Q8 which have control ends commonly connected to a control end of the current mirror input transistor Q1. The constant current is supplied from the plurality of current mirror output transistors Q7 and Q8 to a plurality of operating circuits. Further, at least one of the plurality of current mirror output transistors Q7 and Q8 is equipped with a low pass filter for removing a high-frequency component contained in a current output from the at least one of the plurality of current mirror output transistors Q7 and Q8.

Abstract: A technique for reducing power dissipation and circuit area for a high voltage application includes creating a low-voltage, local power supply for use with local circuitry. In at least one embodiment of the invention, an apparatus includes an output node configured to provide a regulated output voltage. The apparatus includes a variable current source coupled to a first power supply node, wherein the variable current source is configured to provide an output current to the output node based on a control signal on a control node. The apparatus includes a feedback circuit configured to generate the control signal based on a mirrored current. The mirrored current is a mirrored version of a residual current flowing between the output node and a second power supply node. The regulated output voltage has a voltage level less than the voltage level on the first power supply node.

Abstract: An internal voltage generation circuit includes a signal generation unit which generates first and second level signals and first and second control signals from a reference voltage generated by voltage-dividing an internal power and generates first and second driving signals by comparing levels of the internal power and the reference voltage, a driving control unit which receives the first and second level signals and drives the internal voltage in response to an active signal, and a driving unit which receives the first and second driving signals and drives the internal voltage.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a bandgap circuit provided with first and second bipolar transistors that are coupled at a first node and a current mirror circuit provided with third and fourth transistors with respective control terminals coupled at a second node. The electronic circuit further includes a fifth transistor that is bipolar which is coupled to an output terminal of the third transistor where a base of the fifth transistor is coupled to a collector of the second transistor and a sixth transistor that is bipolar that is coupled to an output terminal of the fourth transistor with a base of the sixth transistor coupled to the first node. A control circuit controls a current provided to the bandgap circuit based on an output of the current mirror circuit. A reference voltage output terminal is provided between the control circuit and the bandgap circuit and outputs a reference voltage.

Abstract: A voltage regulator may comprise a regulator output configured to provide a regulated voltage, which may be controlled by an error amplifier based on the regulated voltage and a reference voltage. The error amplifier may control a source-follower stage to mirror a multiple of the current flowing in the source-follower stage into an internal pass device. A voltage developed by the mirror current may control an external pass device configured to deliver the load current into the regulator output. A first resistor may be configured to decouple a load capacitor coupled between the regulator output and reference ground, when the load current is below a specified value. A second resistor may be configured to create a bias current in the internal pass device even when the external pass device is close to cut-off region. A third resistor may be configured to counter the effects of negative impedance at the control terminal of the external pass device caused by the current-gain of the external pass device.

Abstract: A slope compensation circuit includes a first differential pair circuit, a current mirror unit, a first operating current generation circuit, and a transconductance compensation circuit. The first differential pair circuit is connected to a first current source and receives a pair of differential oscillation signals to generate a pair of differential currents corresponding to the differential oscillation signals. The current mirror unit is connected to the first differential pair circuit and mirrors the differential currents. The first operating current generation circuit is connected to the current mirror unit and generates a first operating current including the differential currents. The transconductance compensation circuit stabilizes a quiescent operating point of the first operating current generation circuit and receives the differential oscillation signals to generate an output current multiple times the value of the first operating current.

Abstract: A current mirror arrangement comprising two transistors (11, 12) which are of different conductivity types and are each suitable for outputting a bias current (PBIAS, NBIAS) is specified. A controlled current source (13, 13?) is connected between the two transistors (11, 12) and forms the output of a current mirror (18, 13?). The proposed principle ensures that the output bias signals (PBIAS, NBIAS) match one another in a highly precise manner. The proposed current mirror arrangement may preferably be integrated using CMOS circuit technology.

Abstract: A bandgap voltage reference circuit includes a first circuit portion and a second circuit portion. The first circuit portion generates a voltage complimentary to absolute temperature (VCTAT). The second circuit portion generates a voltage proportional to absolute temperature (VPTAT) that is added to the VCTAT to produce a bandgap voltage reference output. The first circuit portion includes a plurality of delta base-emitter voltage (VBE) generators, connected as a plurality of stacks of delta VBE generators. Each delta VBE generator can include a pair of transistors that operate at different current densities and thereby generate a difference in base-emitter voltages (?VBE). The plurality of delta VBE generators within each stack are connected to one another, and the plurality of stacks of delta VBE generators are connected to one another, such that the ?VBEs generated by the plurality of delta VBE generators are arithmetically added to produce the VPTAT.

Abstract: Exemplary embodiments are directed to a current mirror and method of operation thereof. A method may include biasing a first transistor with a voltage at a gate of a second transistor to cause the first transistor to conduct, wherein the first transistor has a source operably coupled to a drain of a third transistor and a drain operably coupled to a gate of the third transistor. The method may also include providing an input current at the drain of the third transistor. Moreover, the method may include decreasing or increasing a voltage at the gate of the first transistor when a voltage at the gate of the second transistor and the drain of the first transistor respectively decreases or increases. Furthermore, the method may include generating an output current in a drain of a fourth transistor having a gate operably coupled to the gate of the third transistor.

Abstract: A current mirror apparatus includes an input stage receiving an input current, Iin, and no additional bias current. The apparatus includes at least one output stage coupled to mirror the input current as an output current Iout. The input and output stages include insulated gate transistors. A minimum required voltage drop (Vin) across the input stage is approximately 2Von+2Vth, wherein Vth is a threshold voltage of a selected one of the insulated gate transistors, wherein Von is a drain-to-source saturation voltage of the selected transistor. A minimum required voltage drop (Vout) across the output stage is approximately 2Von.

Abstract: Disclosed is a low dropout regulator that uses a load current tracking zero circuit to stabilize a feedback loop to prevent oscillations. The load current tracking zero circuit senses the DC component of the current flowing through the pass transistor of the low dropout regulator and uses the pass transistor current signal to control a multiplicative factor. The multiplicative factor multiplies the AC variations in the output voltage to generate the zero current.

Abstract: A digital-to-analog converter is coupled to a first voltage source and used for converting a digital input into an analog output. The DAC includes a voltage booster providing a first gate-source voltage and a second gate-source voltage to generate a voltage of a first level according to the first voltage source and the first gate-source voltage, and to generate a voltage of a second level according to the voltage of the first level and the second gate-source voltage; and a current-guiding circuit selectively receiving the voltage of the first level or the second level according to the digital input to generate the analog output. The first level and the second level vary with the first voltage source.

Abstract: An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current, while the startup circuit receives the startup current and outputs an output voltage. The startup circuit includes a current mirror, a first NMOS transistor, a second NMOS transistor, diodes, and a third NMOS transistor, and a control circuit. The first and second NMOS transistors are coupled to the current mirror at their sources and are coupled to one another and to the reference circuit at their gates. The diodes are coupled between the gate of the second NMOS transistor and the source of the second NMOS transistor, and the third NMOS transistor is coupled to the source of the second NMOS transistor at its gate (which also provides the output voltage at its source). The control circuit is then coupled to the drains of the first and second NMOS transistors.

Abstract: The present invention discloses a current mirror circuit generating an output current flowing through an output current path according to an input current flowing through an input current path. The current mirror circuit comprises a P type transistor in the output current path, an operational amplifier, and a basic circuit. The operational amplifier has a negative input coupled to a node receiving the input current, a positive input coupled to a drain of the P type transistor, and an output coupled to a gate of the P type transistor. The basic circuit comprises a first transistor in the input current path and a second transistor in the output current path. The first transistor has a gate and a drain coupled together. The second transistor has a gate coupled to the gate of the first transistor.

Abstract: A voltage transformation circuit comprising a first input, a second input, a first output, first and second impedances and a current mirror having master and slave terminals, wherein the first impedance is connected between the first input and the master terminal of the current mirror, the second impedance is connected between the second input and the slave terminal of the current mirror, and the first output is connected to the slave terminal of the current mirror.

Abstract: A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.