With Voltage Or Current Signal Evaluation Patents (Class 324/713)
  • Patent number: 7525323
    Abstract: A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) meter, with which the resistance of the strip of ferromagnetic material over a range of measurement signal frequencies is determined based upon the measured impedance values. The measured impedance values, measurement signal frequencies and selected permeability values are then used in numerical simulations to produce multiple resistance versus frequency curves each of which corresponds to one of the selected permeability values.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: April 28, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Kyuwoon Hwang, Peter I. Smeys, Andrei Papou
  • Patent number: 7521934
    Abstract: A current measurement control system for a power supply system is provided. The current measurement control system includes a load module that estimates a total load of the power supply system. An amplification module selectively determines an amplification factor based on the total load and amplifies a current signal based on the amplification factor. A current measurement module measures current based on the amplified current signal.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: April 21, 2009
    Assignee: Yazaki North America, Inc.
    Inventors: James Leroy Jones, III, Sam Yonghong Guo, Yuanyuan Wu
  • Publication number: 20090095061
    Abstract: An abnormality detection device of a fuel pump reduces costs and prevents detection error or breakdown by making the fuel pressure sensor unnecessary. The abnormality detection device includes an abnormality detection circuit, a fuel pump driving voltage detection unit to detect the voltage value of an abnormality detection circuit, and a meter. The abnormality detection circuit is constituted by the circuit including a resistance disposed between a battery side of the fuel pump motor to drive the fuel pump and a ground side. If the voltage value detected by the fuel pump driving voltage detection unit is larger than the upper limit or lower than the lower limit of the normal range, the warning lamp of the meter flashes and a buzzer makes an alarm sound. The abnormality detection circuit is housed in the fuel pump module disposed in the fuel tank.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Applicant: YAMAHA MARINE KABUSHIKI KAISHA
    Inventors: Kenichi FUJINO, Shigeyuki OZAWA
  • Patent number: 7518377
    Abstract: A signal whose voltage level fluctuates with respect to a high voltage is measured with favorable accuracy.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: April 14, 2009
    Assignee: Advantest Corporation
    Inventors: Seiji Amanuma, Kiyonobu Suzuki
  • Patent number: 7518378
    Abstract: The errors related to the resistance of test conductors and sense/load resistances for a pulse I-V measurement system are determined by making open circuit and through circuit measurements using a combination of DC and pulse instrument measurements.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: April 14, 2009
    Assignee: Keithley Instruments, Inc.
    Inventors: Rajat Mehta, Pete Hulbert
  • Publication number: 20090092033
    Abstract: An electric field sensor includes a substrate having a low resistive semiconductor layer doped with a high-density dopant as the top layer of the substrate, a high resistive semiconductor layer doped with a low-density dopant, the high resistive semiconductor layer located at a partial area on the low resistive semiconductor layer, and a conductive layer located on the high resistive semiconductor layer, wherein a change of an electric field is detected by a change of a current flowing through the low resistive semiconductor layer, the high resistive semiconductor layer, and the conductive layer.
    Type: Application
    Filed: June 12, 2008
    Publication date: April 9, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Simon BUEHLMANN, Hyoung-soo Ko, Ju-hwan Jung, Seung-bum Hong
  • Patent number: 7511515
    Abstract: Novel system and methodology for determining resistance of wires in a communication cable having at least two pairs of wires used for providing power from a power supply device to a powered device. A measuring mechanism may determine DC resistance of the wires before the power supply device applies power to the communication cable.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: March 31, 2009
    Assignee: Linear Technology Corporation
    Inventor: Jacob Herbold
  • Patent number: 7508225
    Abstract: An apparatus, system, and method provide device identification and temperature sensing of a device with a temperature sensing circuit (TSC) within the device. The TSC includes a temperature sensing element (TSE) connected in parallel with a voltage clamping network (VCN) that limits the voltage across the TSE to an identification voltage within an identification voltage range when the voltage is greater than or equal to a lower voltage of the identification voltage range. When a voltage below the lower range is applied to the TSC, the VCN appears as an open circuit and the resistance of the TSC corresponds to temperature. For cost or other concerns, a first TSC may omit the VCN to provide a maximum identification voltage and other TSCs may include VCNs with lower identification voltage ranges.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: March 24, 2009
    Assignee: Kyocera Wireless Corporation
    Inventor: John Philip Taylor
  • Patent number: 7498823
    Abstract: A pair of identical humidity sensors (S1) and (S2) are in the same environment, so that they identically react to humidity effects; a sensing circuit includes an operational amplifier (10), its input (15) receiving from the first sensor (Si) a signal changing with humidity according to a logarithmic law, while the second sensor (S2), inserted in the amplifier feedback, reacts to humidity changes in the same way as the first sensor (Si) and consistently modifies the gain. The output signal (V0) is compensated, and has a substantially linear progression with humidity.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: March 3, 2009
    Assignee: Telecom Italia S.p.A.
    Inventor: Walter Cerutti
  • Patent number: 7495456
    Abstract: Provided are a system and method of determining pulse properties of a semiconductor device. An embodiment of the system includes at least one pair of first and second probes electrically contacting terminals of the semiconductor resistance device, a pulse generator connected to the first probe and outputting pulse signals, an oscilloscope having at least one pair of first and second channels, wherein the pulse electric signal is supplied to the first channel and the first probe and the second channel is connected to the second probe. The oscilloscope calculates a pulse current flowing in terminals of the semiconductor resistance device using the second channel and determines a dynamic resistance of the semiconductor resistance device using the first and second channels.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: February 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hideki Horii, Yong-Ho Ha
  • Publication number: 20090045825
    Abstract: A resistance measuring circuit includes a current generating component, a current control component, and a voltage measurement component. The magnitude of a target resistance can be measured by connecting the target resistance between first and second measurement terminals of the resistance measuring circuit, applying a current generated by the current generating component to the target resistance, and determining the voltage across the target resistance. When no target resistance is connected between the first and second measurement terminals, the current control component controls the current generating component to reduce current consumption of the resistance measuring circuit.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 19, 2009
    Applicant: FLUKE CORPORATION
    Inventor: Benjamin ENG, JR.
  • Patent number: 7489146
    Abstract: A voltage/current (V/I) source includes circuitry having first, second, third and fourth nodes, a first current source electrically connected to the first node, a second current source electrically connected to the second node, where the third and fourth nodes are between the first and second nodes, and an operational amplifier (op-amp) having an output, an inverting input, and a non-inverting input. The output is electrically connected to the third node, and the non-inverting input is electrically connected to a voltage source. A feedback line is between the fourth node and the inverting input.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: February 10, 2009
    Assignee: Teradyne, Inc.
    Inventors: Christian Balke, Cristo da Costa
  • Patent number: 7482820
    Abstract: A sensor for measuring the moisture and salinity of a material is disclosed herein. The sensor preferably includes a soil moisture circuit, a soil salinity circuit and a probe structure. The soil moisture circuit includes a high frequency oscillator, a voltage meter and a reference capacitor. The soil salinity circuit includes a low frequency oscillator, a voltage meter and a reference resistor. A third voltage meter allows for voltage outputs to be measured to calculate soil moisture and soil salinity values.
    Type: Grant
    Filed: August 3, 2008
    Date of Patent: January 27, 2009
    Assignee: Advanced Sensor Technologies, Inc.
    Inventor: Jeffrey Campbell
  • Patent number: 7474106
    Abstract: In a semiconductor device including first and second power supply terminals, a measuring terminal, and at least one trimming detection circuit connected between the measuring terminal and one of the first and second power supply terminals, the trimming detection circuit is constructed by a current supplying element, a series arrangement of a fuse and a switch element, and a determination circuit. The current supplying element and the series arrangement are connected in series between the measuring terminal and the one of the first and second power supply terminals. The determination circuit has an input connected to a node between the current supplying element and the series arrangement and is adapted to determine whether the fuse is in a connection state or in a disconnection state. A voltage at the other of the first and second power supply terminals is applied to the measuring terminal in a normal mode.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: January 6, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kiyoshi Kanno
  • Publication number: 20090001994
    Abstract: In a semiconductor device including first and second power supply terminals, a measuring terminal, and at least one trimming detection circuit connected between the measuring terminal and one of the first and second power supply terminals, the trimming detection circuit is constructed by a current supplying element, a series arrangement of a fuse and a switch element, and a determination circuit. The current supplying element and the series arrangement are connected in series between the measuring terminal and the one of the first and second power supply terminals. The determination circuit has an input connected to a node between the current supplying element and the series arrangement and is adapted to determine whether the fuse is in a connection state or in a disconnection state. A voltage at the other of the first and second power supply terminals is applied to the measuring terminal in a normal mode.
    Type: Application
    Filed: September 2, 2008
    Publication date: January 1, 2009
    Inventor: Kiyoshi Kanno
  • Patent number: 7466119
    Abstract: A sensor circuit includes an AC component pickup circuit and first and second adder circuits or first and second high-pass filters, and specifies a range of normal voltages by an upper-limit voltage formed by adding an upper-limit threshold value to the AC component in the input voltage and by a lower-limit voltage formed by adding a lower-limit threshold value to the AC component in the input voltage. An abnormal offset voltage is detected by judging whether the output voltage of an inverting amplifier circuit is lying in the range of normal voltages.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: December 16, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hajime Ito, Shunji Mase, Takao Tsuruhara
  • Patent number: 7466150
    Abstract: An apparatus for generating a power signal from a load current is described, has a controller with a load current input, a load current output, an intermediate signal output, and a status signal output, an influencing device with an intermediate signal input and a power signal output, and an interruption device with an interrupt input, an interrupt output, and a status signal input. The controller generates a status signal and an intermediate signal depending on the load current, and the interruption device interrupts the power signal if the status signal satisfies a predetermined first condition, and otherwise lets the power signal pass, and the influencing device generates the intermediate signal as the power signal and output the same at the power signal output if the intermediate signal does not satisfy a predetermined second condition, and otherwise generates and output a power signal with a predetermined value.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: December 16, 2008
    Assignee: Infineon Technologies AG
    Inventors: Christian Arndt, Wolfgang Troeger
  • Patent number: 7459913
    Abstract: A method for determining film continuity and growth modes in thin dielectric films includes: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison. The growth metric parameters may include thickness, time, precursor cycles, or temperature.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Joseph F. Shepard, Jr.
  • Patent number: 7459897
    Abstract: The present invention provides a terminator circuit including a potential variation detecting section that detects a variation in a potential at an end point to which an input signal is supplied, and a first current generating section that reduces an overshoot at the end point which is caused by the application of the input signal, by pulling a current from the end point, when the potential variation detecting section detects a rise in the potential at the end point. Here, the potential variation detecting section includes a comparison potential generating section that generates a comparison potential based on a reference potential, and a potential comparing section that compares the comparison potential which has risen in accordance with the rise in the potential at the end point, with the reference potential, and outputs a result of the comparison.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: December 2, 2008
    Assignee: Advantest Corporation
    Inventors: Toshiaki Awaji, Takashi Sekino
  • Publication number: 20080278183
    Abstract: A fuel cell test system including a controller, a housing defining a test chamber, a test subject fuel cell positioned in the test chamber, the test subject fuel cell being in communication with the controller to provide the controller with signals indicative of a performance of the test subject fuel cell, a fuel feed in communication with the test subject fuel cell, the fuel feed having a humidity, a flow rate and a pressure, wherein at least one of the humidity, the flow rate and the pressure of the fuel feed is controllable by the controller, and an oxidant feed in communication with the test subject fuel cell, the oxidant feed having a humidity, a flow rate and a pressure, wherein at least one of the humidity, the flow rate and the pressure of the oxidant feed is controllable by the controller, wherein the controller monitors the performance of the test subject fuel cell in response to the fuel feed and the oxidant feed.
    Type: Application
    Filed: April 7, 2008
    Publication date: November 13, 2008
    Applicant: MOUND TECHNICAL SOLUTIONS, INC.
    Inventors: Douglas A. McClelland, Daniel P. Kramer
  • Publication number: 20080278182
    Abstract: A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Inventors: Kanak B. Agarwal, Ying Liu, Sani R. Nassif
  • Patent number: 7449896
    Abstract: A circuit for sensing a current includes a first upper resistor having a first end coupled to a first end of a sense resistor, the sense resistor being configured to receive an input current. A second upper resistor has a first end coupled to a second end of the sense resistor, so that the sense resistor defines a first potential between the first and second ends of the sense resistor. A first lower resistor is provided between the first upper resistor and the ground. A second lower resistor is provided between the second upper resistor and the ground. An amplifier has a first input node and a second input node, the first input node being coupled to a node between the first upper resistor and the first lower resistor. The second input node is coupled to a node between the to the second upper resistor and the second lower resistor. The first and second input nodes defines a second potential corresponding to the first potential.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: November 11, 2008
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 7449897
    Abstract: A device includes a light emitter, a current sensing resistance, a current generator, and detection circuitry. The current generator is connected to the light emitter and to the current sensing resistance. During a normal operating mode of the device, the current generator regulates current flow through the light emitter. In a test mode, the current generator regulates current flow through the current sensing resistance. The detection circuitry, during the test mode, detects when current flow through the current sensing resistance is outside an expected range.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: November 11, 2008
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Vincent C. Moyer, Michael J. Brosnan, Shan Chong Tan
  • Patent number: 7443177
    Abstract: A method of determining material parameters associated with a conductor using four points includes injecting and extracting alternating current into the plate using current-carrying wires operatively connected to two of the four points, measuring potential drop between the remaining two of the four points, and calculating the material parameters. The conductor can be of a homogenous material, a stratified material, or other type of material. The conductor can have any number of geometries, including that of a plate, a cylinder, a tube, a stratified cylinder or other shape.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: October 28, 2008
    Assignee: Iowa State University Research Foundation, Inc.
    Inventor: Nicola Bowler
  • Patent number: 7443155
    Abstract: A voltage detecting apparatus with a capacitor having a switch for detecting a voltage of a direct-current power source, which can detect a malfunction of the switch without additional parts and effects to a measurement time in a normal condition, is provided. When a microcomputer measures a voltage between both terminals of a capacitor plural times, the sampled voltages are at most a prescribed threshold value, and a voltage decreases at least a prescribed difference of voltages in sampling order (each of all measured voltages between both terminals decreases at least a potential deference from a voltage measured previously in sampling order). Furthermore, when the voltage between both terminals of the capacitor becomes 0 volt in condition that a fifth switch SW5 is opened, it is judged that the fifth switch is in an abnormal condition.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 28, 2008
    Assignee: Yazaki Corporation
    Inventor: Yoshihiro Kawamura
  • Patent number: 7443171
    Abstract: A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench capacitor pair has a first deep trench capacitor and a second deep trench capacitor connected in parallel. A first transistor has a first terminal electrically coupled to the first deep trench capacitor and a control terminal electrically coupled to a first word line. A second transistor has a first terminal electrically coupled to the second deep trench capacitor and a control terminal electrically coupled to a second word line. First and second bit lines are electrically coupled to the first and second transistors respectively. The first and second bit lines are separated and the first and second word lines are perpendicular to the bit line regions.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: October 28, 2008
    Assignee: Nanya Technology Corporation
    Inventor: Yu-Chang Lin
  • Publication number: 20080252307
    Abstract: A method and apparatus are provided for determining resistive power loss through a channel between Power Sourcing Equipment (PSE) and a Powered Device (PD). The method includes (1) receiving indication that a PSE signal measurement is available from the PSE or a PD signal measurement is available from the PD, (2) selecting, as an input parameter to a processing operation, at least one of the PSE signal measurement or the PD signal measurement, (3) performing the processing operation to calculate a resistance value indicative of the resistive power loss through the channel between the PSE and PD based on the input parameter, and (4) outputting the resistive power loss value as a result of carrying out the processing operation.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Applicant: Cisco Technology, Inc.
    Inventor: Frederick R. Schindler
  • Publication number: 20080252308
    Abstract: A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
    Type: Application
    Filed: June 23, 2008
    Publication date: October 16, 2008
    Applicant: International Business Machines Corporation
    Inventors: Jean Audet, Louis B. Capps, Glenn G. Daves, Anand Haridass, Ronald E. Newhart, Michael J. Shapiro
  • Patent number: 7436189
    Abstract: A real-time load current detecting circuit composed of a power supply circuit, a delay circuit, a current sensing circuit, and a current feedback circuit. The power supply circuit is adapted for providing the CPU with a power source. The delay circuit includes a resistor and a capacitor, connected to the power supply circuit. The current sensing circuit includes a comparison circuit connected to the delay and power supply circuits. The current feedback circuit includes a feedback current source and a resistor, connected to the current sensing circuit. The feedback current source is adapted for mirroring a current sensed by the current sensing circuit. In light of this, the current can be accurately monitored and detected and there is hardly inaccuracy for the detection of the current.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 14, 2008
    Assignee: Universal Scientific Industrial Co., Ltd.
    Inventors: Chiu-Yi Pai, Hsiang-Lung Yu
  • Patent number: 7429866
    Abstract: A method for improved cable resistance measuring is provided including coupling a measurement test device including a master unit and a remote unit, via at least one connector, to at least one network cable and determining a terminating impedance using field calibration. The method additionally including transmitting an AC signal across the network cable for determining a resistance of the network cable, and measuring a length of the network cable. The method still further including measuring a capacitance of the network cable, and measuring an impedance of the network cable terminated by the measurement test device. The method additionally including extracting the resistance of the network cable from the impedance measurement, and correcting for error in at least one of capacitance, termination resistance, and nominal cable effects for a corrected resistance value.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: September 30, 2008
    Assignee: Avo Multi-Amp Corporation
    Inventor: Gerald Wayne Beene
  • Publication number: 20080221805
    Abstract: A multi-channel lock-in amplifier system for use in cell analysis is disclosed. The system may include a cartridge having one or more flow cells with each flow cell containing a cell for analysis. An oscillating electric field may be applied across each flow cell at one or more excitation frequencies in order to detect the responses of the cell either in electrical impedance at frequencies that provide a non-linear response.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 11, 2008
    Inventor: David Richard Andrews
  • Patent number: 7423438
    Abstract: Provided are a method and apparatus for measuring body fat using current electrodes and voltage electrodes. The method includes continually detecting a voltage drop across the voltage electrodes by smoothly raising a contact pressure applied to the electrodes; determining a threshold contact pressure with reference to the detected voltage drop depending on variation of the contact pressure, the voltage drop across the voltage electrodes not increasing under the threshold contact pressure even when the contact pressure increases; comparing a detected contact pressure with the threshold contact pressure; detecting a measurement voltage across the voltage electrodes only when the detected contact pressure is larger than the threshold contact pressure; and compensating the measurement voltage for a threshold contact voltage corresponding to the threshold contact pressure and calculating a body fat value corresponding to the compensated measurement voltage.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: September 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-kook Park, Kyung-Ho Kim, Jeong-Je Park
  • Patent number: 7420119
    Abstract: An exemplary subterranean hub for an outdoor system for distributing electrical power to a plurality of fixtures is provided, the hub having a body, a plurality of electrical connectors disposed on the body and adapted to accept mating connectors from a corresponding fixtures, means for electrically coupling an external power source to the electrical connectors, and a depth reference marker, connected to the body and adapted to provide a visual verification that the hub is buried at a sufficient depth during installation of the hub.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: September 2, 2008
    Assignee: The L.D. Kichler Co.
    Inventors: Joseph John Janos, John Joseph Ascherl, Michael William Briggs, Raymond J. Fritz, Richard Williams
  • Patent number: 7420378
    Abstract: A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: September 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Louis B. Capps, Jr., Glenn G. Daves, Anand Haridass, Ronald E. Newhart, Michael J. Shapiro
  • Publication number: 20080204034
    Abstract: The present invention is directed to an electrical wiring inspection system that includes a user interface device including processor circuitry, a user interface, and a first communications interface. The first communications interface is configured to transmit configuration data related to a plurality of electrical test procedures and receive test data corresponding to a plurality of electrical parameters. A branch circuit analysis device is configured to be coupled to the user interface device via the first communications interface and at least one branch circuit by at least one test connector. The branch circuit analysis device includes processor circuitry, branch circuit test circuitry configured to perform one or more of the plurality of electrical test procedures, and a second communications interface configured to transmit and receive configuration data related to a plurality of electrical test procedures and transmit and receive test data corresponding to a plurality of electrical parameters.
    Type: Application
    Filed: May 8, 2008
    Publication date: August 28, 2008
    Applicant: Pass & Seymour, Inc.
    Inventor: Frederick K. Blades
  • Publication number: 20080204054
    Abstract: A system for obtaining an accurate, real-time determination of the characteristic impedance of a length of a power line measures the operating conditions (e.g., voltage and current) for at least two locations on the power line. These measurements are synchronized so that they represent the same instant of time. The data obtained from the synchronized measurements are fitted to a circuit model of the power line to obtain a characteristic impedance for the power line according, which can be used to increase the efficiency of the use of the power line and to perform real-time assessment of the power line.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Applicant: OSISOFT, INC.
    Inventor: Charles H. Wells
  • Publication number: 20080204040
    Abstract: One disclosed method is to automate testing for transmission path impedance conditions on a circuit board. The method can include transmitting a plurality of electrical pulses on a transmission path utilizing an on-board transmitter, the electrical pulses can have a time period and the transmission path can have impedance mismatches to reflect energy of the electrical pulse back towards the on-board transmitter. After the pulse is transmitted, a voltage of the reflected energy can be compared with a reference voltage at different time intervals. A single bit can be acquired for each voltage/time sample and the bits can be sequentially stored in a shift register. The digital data that is stored in the shift register can be compared to existing data in memory to determine a quality of the transmission path of the printed circuit board.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Inventor: Harry Muljono
  • Patent number: 7417443
    Abstract: A method of determining an effective resistance between a power sourcing equipment and a powered device, the powered device exhibiting an interface and an operational circuitry, the method comprising: prior to connecting power to the operational circuitry of the powered device, impressing two disparate current flow levels (I1, I2) between the power sourcing equipment and the powered device; measuring the voltage at the powered device interface (VPD1, VPD2) responsive to each of the impressed disparate current levels; measuring the voltage at the power sourcing equipment (VPSE1, VPSE2) responsive to each of the impressed disparate current levels; and determining the effective resistance between the power sourcing equipment and the powered device responsive to the VPD1, VPD2, VPSE1, VPSE2, I1 and 12.
    Type: Grant
    Filed: January 7, 2007
    Date of Patent: August 26, 2008
    Assignee: Microsemi Corp. - Analog Mixed Signal Group, Ltd.
    Inventors: Dan Admon, Shimon Elkayam
  • Patent number: 7415312
    Abstract: A process module tuning method characterizes a process module by gathering data using a process condition measuring device to measure process outputs while inputs are excited. The data is used to identify a dynamic process model. The dynamic process model is then be used to determine process input settings that will produce desired outputs. For multi-zone process modules, the interactions between zones may be modeled.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: August 19, 2008
    Inventors: James R. Barnett, Jr., Mark K. Ekblad, Jeffrey M. Parker
  • Patent number: 7411407
    Abstract: A test system includes a circuit assembly having an IC and an external circuit. The IC includes test circuitry used to observe data indicative of target resistances in the external circuit. The test system evaluates the data to determine target resistance values. A first embodiment measures two output voltages responsive to a time varying reference voltage. The two output voltages can be used to determine resistance values in the external circuit. A second embodiment enables logic contention on the IC, controllably fixes a pull-down element on the IC, and controllably sweeps a pull-up element on the IC until the voltage at a node between the pull-down and pull-up elements and coupled to an external circuit exceeds a reference voltage.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 12, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Jeffrey R. Rearick, Jacob L. Bell
  • Publication number: 20080186035
    Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATION
    Inventors: Robert L. Franch, Keith A. Jenkins
  • Patent number: 7408364
    Abstract: A sensor for measuring the moisture and salinity of a material is disclosed herein. The sensor preferably includes a soil moisture circuit, a soil salinity circuit and a probe structure. The soil moisture circuit includes a high frequency oscillator, a voltage meter and a reference capacitor. The soil salinity circuit includes a low frequency oscillator, a voltage meter and a reference resistor. A third voltage meter allows for voltage outputs to be measured to calculate soil moisture and soil salinity values.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: August 5, 2008
    Assignee: Advanced Sensor Technologies, Inc.
    Inventor: Jeffrey Campbell
  • Patent number: 7405579
    Abstract: The present invention is to provide a voltage detector having a common communication line for reducing a manufacturing cost. A low voltage line CPU transmits a detection instruction including an assignment of one address among a plurality of blocks. The detection instruction is branched by a transmitting bus line for concurrently transmitting to a plurality of voltage detector units. When one of the voltage detector units receives the detection instruction with the address being same as a self-address thereof, the voltage detector unit detects output voltages of unit cells and transmits the detected result to the low voltage line CPU. When the received address is not the self-address, the voltage detector unit does not transmit the detected result.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: July 29, 2008
    Assignee: Yazaki Corporation
    Inventors: Hajime Okamoto, Satoshi Ishikawa, Ryosuke Kawano
  • Publication number: 20080164890
    Abstract: A method of determining an effective resistance between a power sourcing equipment and a powered device, the powered device exhibiting an interface and an operational circuitry, the method comprising: prior to connecting power to the operational circuitry of the powered device, impressing two disparate current flow levels (I1, I2) between the power sourcing equipment and the powered device; measuring the voltage at the powered device interface (VPD1, VPD2) responsive to each of the impressed disparate current levels; measuring the voltage at the power sourcing equipment (VPSE1, VPSE2) responsive to each of the impressed disparate current levels; and determining the effective resistance between the power sourcing equipment and the powered device responsive to the VPD1, PPD2, VPSE1, VPSE2, I1 and I2.
    Type: Application
    Filed: January 7, 2007
    Publication date: July 10, 2008
    Applicant: POWERDSINE, LTD.
    Inventors: Dan ADMON, Shimon ELKAYAM
  • Publication number: 20080157788
    Abstract: A method for testing voltage endurance of a electronic component, includes: generating an oscillating signal; amplifying the oscillating signal; transforming the amplified oscillating signal to generate a transformed signal; blocking a negative voltage of the transformed signal to generate a test signal to be transmitted to the electronic component; and detecting electrical characteristics of the electronic component to generate result data.
    Type: Application
    Filed: August 10, 2007
    Publication date: July 3, 2008
    Applicants: HONG FU JIN PRECISION INDUSTRY (Shenzhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: SHIH-FANG WONG, TSUNG-JEN CHUANG, JUN LI
  • Patent number: 7394264
    Abstract: The invention relates to a device for measuring current in an inductor and being connected in parallel with said inductor. The device includes a network in parallel with the inductor and connected to the terminals A and B comprising a resistor R2 in series with a resistor R1 in parallel with a capacitor C1; a voltage offset circuit having a DC voltage generator E connected in parallel with an offset resistor (Roffset) in series with two parallel resistors R3 and R4, the positive pole of the voltage source being connected to terminal B of the inductor; a temperature compensation circuit comprising a current source controlled as a function of the temperature, one of the two terminals of the current source being connected to the negative pole of the generator E, the other terminal of the current source being connected to different points of the measurement device.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: July 1, 2008
    Assignee: Thales
    Inventors: Flavien Blanc, Christophe Taurand
  • Patent number: 7391226
    Abstract: The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 24, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark W. Michael, Raymond G. Stephany
  • Publication number: 20080143352
    Abstract: A titanium oxide extended gate field effect transistor (EGFET) device and fabricating method thereof. Titanium oxide is formed on an EGFET by sputtering, coating a detection membrane therefor. Current-voltage relationships at different pH values are also measured via a current measuring system. Sensitivity parameter of the titanium oxide EGFET is calculated according to a relationship between a pH value and a gate voltage.
    Type: Application
    Filed: February 26, 2008
    Publication date: June 19, 2008
    Applicant: NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jung-Chuan Chou, Hung-Hsi Yang
  • Patent number: 7388387
    Abstract: An electronic circuit and method to determine a resistance value of a resistive element. The circuit includes a current source coupled in series with the resistive element. The current source is configured to force a predetermined value of current through the resistive element and includes a transconducting device coupled to the current source. The transconducting device is configured to sense a voltage across the resistive element and transform the voltage into an output current of the transconducting device such that the output current is not dependent upon any other terminal voltages of the transconducting device.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: June 17, 2008
    Assignee: Stratosphere Solutions, Inc.
    Inventor: Terry James Bordelon, Jr.
  • Patent number: 7385406
    Abstract: The present invention is directed to an electrical wiring inspection system. The system includes an electrical measurement apparatus having at least one load center connector configured to couple the electrical measurement apparatus to a load center, at least one branch circuit connective device configured to couple the electrical measurement apparatus to a portion of a branch circuit, and at least one electrical measurement circuit disposed between the at least one load center connector and the at least one branch circuit connective device. The at least one electrical measurement circuit is configured to perform a series of electrical test procedures to obtain a plurality of electrical parameters. A portable computing device (PCD) includes processing circuitry, a user interface coupled to the processing circuitry, and at least one communications interface configured to couple the portable computing device to the electrical measurement apparatus.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: June 10, 2008
    Assignee: Pass & Seymour, Inc.
    Inventor: Frederick K. Blades