With Voltage Or Current Signal Evaluation Patents (Class 324/713)
  • Patent number: 7847573
    Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the lines of wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals. The connection section may include a performance board to which the device under test is mounted, where the lines of wiring are connected with each other on the performance board.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: December 7, 2010
    Assignee: Advantest Corporation
    Inventor: Masatoshi Ohashi
  • Patent number: 7839154
    Abstract: A system and method of classifying a high powered device (PD) with an increased current limit includes: connecting a voltage to the PD, measuring current through a classification resistor connected to the PD, and determining a PD classification signature based on the current according to classification steps such that a minimum classification step includes a minimum current of 0 mA and a maximum classification step includes a maximum current beyond a predetermined current limit. The system includes a PSE, voltage source, PD classification resistor, and PD voltage, connected to the P. An alternative embodiment further includes a discrete classification circuit and discrete classification resistor to be used to measure the current for classification purposes instead of the PD classification resistor when the PD and PD classification resistor do not support power classification under the classification scheme.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: November 23, 2010
    Assignee: Broadcom Corporation
    Inventors: Asif Hussain, Manisha Pandya
  • Publication number: 20100283491
    Abstract: A double-clamp earth tester device, having a voltage-inducing transformer (VT) (30), a current-sensing transformer (CT) (32), a voltage source adapted to supply a voltage across a primary winding (31) on the VT core (44) and a signal processing unit (35) adapted to measure a resultant signal output from a secondary winding (33) on the CT core (46), is susceptible to errors induced by electromagnetic interference between the cores (44, 46) of the two transformers. Previously, the effects of this interference have been mitigated by surrounding one or both cores (44, 46) with electromagnetic shielding (42). This had lead to devices having a bulky head portion and attendant difficulties in accessing sites having restricted access (52). These problems have been overcome by providing means to modify the signal output form the secondary winding (33).
    Type: Application
    Filed: May 5, 2010
    Publication date: November 11, 2010
    Applicant: MEGGER LIMITED
    Inventors: Stanislaw Zurek, Stephen Mynott, Daniel Scott Hammett, Owen Thurstan Gosford
  • Publication number: 20100277183
    Abstract: A one sheet test device and a method of testing using the same that can prevent a change of current characteristics due to a failure panel by measuring a current of normal panels except for the failure panel, when testing a one sheet substrate that includes panels, first wires that are arranged in a first direction between and connected to the panels, second wires that are arranged in a second direction different from the first direction between and connected to the panels. The test device includes voltage application units that are connected to the first and second wires, respectively, to apply a selected one of the first voltage and the second voltage to the corresponding wires; and a test unit that controls the voltage application units to measure an on-current and off-current of each of the panels.
    Type: Application
    Filed: August 20, 2009
    Publication date: November 4, 2010
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventor: Sung-Kook KIM
  • Patent number: 7825672
    Abstract: Methods to determine an instantaneous resistance value of an electric circuit and a measurement system to determine an instantaneous resistance value of an electric circuit are disclosed. Exemplary embodiments of the method measure an in-situ instantaneous voltage of the circuit and an in-situ instantaneous current of the circuit and calculate the instantaneous resistance. Optional temperature measurement can be included in the method and the calculated instantaneous resistance related to the measured temperature. The method can be applied to phase angle fired loads and to zero-cross (time proportioned) loads.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: November 2, 2010
    Assignees: MRL Industries, Inc., Sandvik Intellectual Property AB
    Inventors: Kevin B. Peck, Noel Johnson, Björn Å. Larsson, Pontus K. H. Nilsson
  • Patent number: 7819283
    Abstract: A strip ejection system for holding and ejecting a strip is provided. The system includes a body and a strip movement section. The strip moving section includes all elements of the system that are involved with moving the strip, including a pressing element for pressing against the strip to move the strip from a first position to a second position. The pressing element is the only element of the strip movement section that is movable relative to the body.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: October 26, 2010
    Assignee: Universal Biosensors Pty Ltd
    Inventors: Garry Chambers, Alastair Hodges, David Sayer
  • Patent number: 7818591
    Abstract: A method and apparatus are provided for determining resistive power loss through a channel between Power Sourcing Equipment (PSE) and a Powered Device (PD). The method includes (1) receiving indication that a PSE signal measurement is available from the PSE or a PD signal measurement is available from the PD, (2) selecting, as an input parameter to a processing operation, at least one of the PSE signal measurement or the PD signal measurement, (3) performing the processing operation to calculate a resistance value indicative of the resistive power loss through the channel between the PSE and PD based on the input parameter, and (4) outputting the resistive power loss value as a result of carrying out the processing operation.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: October 19, 2010
    Assignee: Cisco Technology, Inc.
    Inventor: Frederick R. Schindler
  • Patent number: 7804310
    Abstract: A multi-source MOS transistor includes a sense MOS transistor and a load MOS transistor, and is connected to a load. A current detection portion has a negative input offset voltage characteristic, and detects a first sense current in a state where it is connected to the power supply and the sense MOS transistor and a second sense current in a state where it is connected to the sense MOS transistor and the load MOS transistor. A calculation control portion calculates a load current based on the first sense current and the second sense current such that the effect of the input offset voltage in the current detection portion is cancelled.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: September 28, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kenji Amada
  • Patent number: 7804288
    Abstract: A method and a corresponding appliance for measuring the output current of a frequency converter, the frequency converter including a network bridge that can be connected to an AC network, a controllable three-phase load bridge that can be connected to an AC load, and a DC intermediate circuit between them, the DC intermediate circuit including a filter capacitor that includes controllable semiconductor switches in each phase and that are controlled by pulse-width modulation, and in which the currents of the output phases are determined based on measured samples of the current of the filter capacitor of the DC intermediate circuit.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: September 28, 2010
    Assignee: Vacon Oyj
    Inventors: Jaakko Ollila, Risto Komulainen, Lasse Kortelahti
  • Patent number: 7799237
    Abstract: A plasma processing apparatus includes a plasma reaction chamber in which a plasma is generated for processing. First and second electrodes are located in the chamber for generating the plasma. First and second RF power sources provide RF power to the first and second electrodes, respectively. The apparatus also includes first and second impedance matching circuits through which the RF power is respectively provided from the first and second RF power supplies to the first and second electrodes. A first plasma controller monitors plasma density and, in response thereto, adjusts the RF power supplied by the first RF power source to the first electrode to achieve a given plasma density. A second plasma controller monitors the ion energy of plasma species impinging on a semiconductor structure associated with the second electrode and, in response thereto, adjusts the RF power supplied by the second RF power source to the second electrode to achieve a given ion energy.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: September 21, 2010
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Seiji Iseda
  • Patent number: 7800380
    Abstract: A circuit for controlling a voltage across a device and permitting measurement of a current through the device includes a sense impedance in series combination with, the device, a sensed voltage measured across the sense impedance being representative of the current through the device; a capacitive stability element in parallel combination with the sense resistance, the capacitive stability element being virtually absent by connection to a virtual version of the sensed voltage when the device has a first capacitance and being present when the device has a second capacitance, the second capacitance being larger than the first capacitance.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: September 21, 2010
    Assignee: Keithley Instruments Inc.
    Inventors: John G. Banaska, Gregory Roberts
  • Publication number: 20100225340
    Abstract: A displacement sensor element and a haptic sensor arrangement using two or more displacement sensor elements are provided. The arrangements can be used for real-time capture of the shape of haptic deformation of the sensor arrangement. Although examples described in detail herein are primarily directed to tactile applications, the sensor can be used in the machine, robotic and medical fields where a sensor of this type can usefully be applied where only machine or computer controlled robotic elements are interacting, particularly if the machines or robotic elements are being used in human like applications but other force measurement applications are possible.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 9, 2010
    Inventors: Ross Travers Smith, Bruce Hunter Thomas, Wayne Piekarski
  • Patent number: 7786736
    Abstract: Methods and structural defect detectors for detecting a structural defect in composites are presented. An exemplary method includes forming a nanocomposite including a plurality of nanotubes mechanically aligned in a principal direction within a polymer matrix. A voltage is applied to the nanocomposite and a resistance of the nanocomposite is measured using the applied voltage to detect the structural defect. An exemplary structural defect detector includes a nanocomposite including a plurality of mechanically aligned nanotubes within the polymer matrix, electrodes coupled to the nanocomposite, a voltage source for applying a voltage to the electrodes, and a resistance detector for measuring a resistance of the nanocomposite that allows identification of a structural defect. The plurality of nanotubes form a conducting percolating network of sensors.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: August 31, 2010
    Assignee: University of Delaware
    Inventors: Erik T. Thostenson, Tsu-Wei Chou
  • Patent number: 7777506
    Abstract: A high-voltage generator of an X-ray apparatus comprises a high-voltage measurement device. The measurement device comprises a compact component comprising both the measurement resistor and a film capacitor used both to protect said resistor and eliminate the parasitic effects induced by parasitic capacitances of the generator. The film capacitor is made in insulating films by a sequence of metalized strips and insulating strips. The films are positioned relative to one another in such a way that the film capacitor is formed by series-mounted discrete capacitors. To this end, between two successive films, the width of the bottom strips of the film crosses two metalized strips of the top film.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: August 17, 2010
    Assignee: General Electric Company
    Inventors: Philippe Ernest, Laurence Abonneau-Casteignau, Florent Liffran
  • Patent number: 7777505
    Abstract: A nanopore device includes a membrane having a nanopore extending there through forming a channel from a first side of the membrane to a second side of the membrane. The surface of the channel and first side of the membrane are modified with a hydrophobic coating. A first lipid monolayer is deposited on the first side of the membrane, and a second lipid monolayer is deposited on the second side of the membrane, wherein the hydrophobic coating causes spontaneous generation of a lipid bilayer across the nanopore orifice. Sensing entities, such as a protein ion channel, can be inserted and removed from the bilayer by adjusting transmembrane pressure, and adapter molecules can be electrostatically trapped in the ion channel by applying high transmembrane voltages, while resistance or current flow through the sensing entity can be measured electrically.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: August 17, 2010
    Assignee: University of Utah Research Foundation
    Inventors: Henry S. White, Ryan J. White, Eric N. Ervin
  • Patent number: 7772856
    Abstract: A junction-current probe is provided which can measure a current flowing in a junction port adapted to connect a circuit board or an electronic apparatus to a chassis under the condition that the circuit board or electronic apparatus is packaged to the chassis. Structurally, the current probe has a circular or rectangular insulator having a hole in the center, a coiled conductor wire for converting linkage flux into voltage, an insulating member for preventing the insulator from making electrical contact with surroundings, an extraction lead for connecting opposite ends of the conductor wire to a cable and the cable for connection to a measurement unit. The current probe is reduced in thickness within in a range in which the condition of packaging to the chassis can remain unchanged.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: August 10, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroki Funato, Takashi Suga
  • Patent number: 7772857
    Abstract: A signal injection unit injects a test signal at a main frequency between a reference point of an electric circuit and ground, where the electric circuit is connected with the facility and injects another test signal at a second main frequency between a reference point of the electric circuit and ground. A signal conversion unit measures first and second response voltages and first and second response currents in the electric circuit, where the response voltages and the response currents result from the test signals. A processing device determines impedances to ground of the facility from the response voltages and the response currents, analyses impedances to ground of the facility, where this analysing includes comparing each determined impedance to ground with a predetermined value, and determines a safety state of the disconnected electrical facility based on the analysed impedances to ground.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 10, 2010
    Assignee: ABB Research Ltd.
    Inventor: Gabriel Olguin
  • Patent number: 7772818
    Abstract: One embodiment of the present invention provides an apparatus that measures the average-output-current produced by a switching regulator within an electronic device. The apparatus includes current-sensing-circuitry coupled to a switching field-effect-transistor (FET) within the switching regulator, wherein the current-sensing-circuitry is configured to bypass a small sense current from the conducting current of the switching-FET according to a sense ratio, wherein the conducting current is controlled by a control signal for the switching regulator. The apparatus also includes a current-to-voltage-converter coupled to the current-sensing-circuitry which is configured to convert the sense current into a sense voltage. The apparatus further includes voltage-averaging-circuitry which is configured to produce an average-sense-voltage from the sense voltage. This sense voltage is coupled to the input of the voltage-average-circuitry through a switch, which is gated by the control signal.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: August 10, 2010
    Assignee: Apple Inc.
    Inventor: Eric Smith
  • Publication number: 20100194413
    Abstract: The invention relates to a method of determining an impedance function IF of a load LS driven by an amplifier AM, said method comprising the steps of providing a digital audio signal DAS to said amplifier AM, measuring one of either a current signal representation CSR of current provided to said load LS by said amplifier AM or a voltage signal representation VSR of voltage provided to said load LS by said amplifier AM, determining a digital signal representation DSR on the basis of said digital audio signal DAS, and determining said impedance function IF of said load LS on the basis of said digital signal representation DSR and said measured one of either said current signal representation CSR or said voltage signal representation VSR.
    Type: Application
    Filed: July 16, 2007
    Publication date: August 5, 2010
    Applicant: LAB.GRUPPEN AB
    Inventors: Klas Åke Dalbjörn, Kim Rishøj Pedersen
  • Patent number: 7765673
    Abstract: A method and system for improving power distribution and/or current measurement on a printed circuit board is disclosed. According to the invention, a first power plane adapted for current measurement includes a first segment to which a current source is connected and a second segment to which other devices may be connected, forming the current load. A third segment is used to measure the current between the first segment and the second segment through two vias that link two points of the third segment to, preferably, two pads of the external layer. In a preferred embodiment, vias are connected to the first segment so that current flow in the third segment is linear, to improve and simplify current determination. The resistivity between the pair of vias may be computed or estimated using calibrated currents.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jean-Francois Fauh, Claude Gomez, Andre Lecerf, Denis G. Roman
  • Patent number: 7768274
    Abstract: A voltage tolerance measuring apparatus configured to measure voltage tolerance of a motherboard includes a first connector configured to connect with a power connector of a computer power supply, a second connector configured to connect with a power connector of the motherboard, and a measuring circuit having an adjustable direct current (DC) power supply and a switch circuit. The adjustable DC power supply is connected to power pins of the second connector via the switch circuit. The switch circuit is connected to a power-on pin of the second connector. When the switch circuit receives a power-on signal of the motherboard via the power-on pin of the second connector, the switch circuit controls the adjustable DC power supply to supply power to the power pins of the second connector.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: August 3, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Ying Chen, Jin-Liang Xiong
  • Publication number: 20100188894
    Abstract: A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Hari Rao, Sei Seung Yoon, Xiaochun Zhu, Mohamed Hassan Abu-Rahma
  • Publication number: 20100182024
    Abstract: A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Applicant: Broadcom Corporation
    Inventor: James Yu
  • Patent number: 7755371
    Abstract: A system for obtaining an accurate, real-time determination of the characteristic impedance of a length of a power line that measures the operating conditions (e.g., voltage and current) for at least two locations on the power line. These measurements are synchronized so that they represent the same instant of time. The data obtained from the synchronized measurements are fitted to a circuit model of the power line to obtain a characteristic impedance for the power line, which can be used to increase the efficiency of the use of the power line and to perform real-time assessment of the power line.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: July 13, 2010
    Assignee: OSIsoft, Inc.
    Inventor: Charles H. Wells
  • Patent number: 7755370
    Abstract: An exemplary method for examining bonding resistance includes providing a first electronic component having a first and second reference pins. A second electronic component having a third and fourth reference pins is also provided. A first input voltage is applied to the first reference pin. A bias resistor connected between the third reference pin and ground is provided, with the third reference pin serving as an output for providing a first reference voltage. The first reference voltage is measured. Bonding resistance between the first reference pin and the third reference pin is evaluated according to the measured first reference voltage.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: July 13, 2010
    Assignee: Innolux Display Corp.
    Inventor: De-Ching Shie
  • Publication number: 20100171517
    Abstract: An impedance measurement method for circuits that has multiple power supply ports and a common ground shared by the multiple power supply ports, that includes finding multiple mutual impedances; finding approximate values for the ground impedance from the multiple mutual impedances; calculating multiple power supply port impedances from the approximate ground impedance values; and generating an equivalent circuit for the applicable circuit based on the ground impedances.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 8, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Ryuichi Oikawa
  • Publication number: 20100173212
    Abstract: In a fuel cell system, a load control unit causes transistor elements to be operated at a timing of every predetermined elapsed periods, so that specific currents having ? and 2? amperes are output. In a degradation detection unit, output voltages Va, Vb are obtained from the ? and 2? amperes, an inclination R(=dv/dI) corresponding to output a resistance Rdmfc is acquired from a difference dv between the output voltages Va, Vb, and an open circuit voltage OCV is obtained from a voltage (Va+dv) obtained by adding the difference dv to the voltage Va. In a judgment unit, the inclination R(=dv/dI) and the voltage OCV are compared with threshold values, respectively, so that the a detection signal indication a degradation of a fuel cell power generation unit is output. Thus, it is possible to detect the cell degradation and to drive a load constantly and stably.
    Type: Application
    Filed: March 18, 2010
    Publication date: July 8, 2010
    Inventors: Kiyoshi SENOUE, Hidenori Suzuki
  • Publication number: 20100164516
    Abstract: A method and a device for monitoring at least one output stage for an inductive load using a current regulator and an analysis device are described. A short circuit to a power supply or to ground is detected by comparing at least one current value in a switching phase of the at least one output stage with at least one current value in a free-wheeling phase of the at least one output stage.
    Type: Application
    Filed: April 30, 2007
    Publication date: July 1, 2010
    Applicant: ROBERT BOSCH GMBH
    Inventors: Christian Lammers, Jochen Neumeister, Hans Raub, Steffen Reinhardt, Danilo Marcato
  • Patent number: 7746086
    Abstract: Disclosed herein are a noncontact single side probe and an apparatus and method for testing open and short circuits of pattern electrodes. By feeding power to one end of each of the pattern electrodes and sensing an electrical variation value using a noncontact type single side probe device including an exciter electrode and a sensor electrode as a single module, the open and short circuits of pattern electrodes can be tested by one scanning process. Since the open and short circuits of the pattern electrodes are tested using the noncontact type single side probe device, the pattern electrode can be prevented from being damaged due to a contact failure or pressurized contact and the life span of the probe device can increase compared with a contact type probe device.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: June 29, 2010
    Assignee: Microinspection, Inc.
    Inventors: Tak Eun, Seong Jin Kim, Hee Dok Choi, Dong Jun Lee, Jong In Park, Woo Chul Cho
  • Patent number: 7741859
    Abstract: The invention relates to a method for determining the sealing of a substance on a support by determining the electrical noise.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 22, 2010
    Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventor: Moritz Völker
  • Patent number: 7739573
    Abstract: A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jonathan J. DeMent, Sang H. Dhong, Gilles Gervais, Alain Loiseau, Kirk D. Peterson, John L. Sinchak
  • Patent number: 7733098
    Abstract: This invention generally relates to saturation detection circuits, in embodiments for substantially lossless detection of saturation of power switches in power integrated circuits. We describe a saturation detection circuit for detecting saturation of a power semiconductor device, the circuit including a said power semiconductor device having an input terminal and an output terminal, a second semiconductor device connected across said input and output terminals of the power semiconductor device, and a circuit responsive to a current flowing through the second semiconductor device to detect the saturation of the power semiconductor device.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: June 8, 2010
    Assignee: Cambridge Semiconductor Limited
    Inventors: Vinod A. Lalithambika, Niek van der Dui{grave over (j)}n Schouten, A. Johannes Schiff
  • Publication number: 20100127720
    Abstract: A first resistor, a second resistor, a transistor, and a third resistor connected in series between a ground potential and an output terminal of a power circuit are provided. In addition, a current-detecting resistor is inserted in series between a high-voltage site and an output terminal of a power circuit that supplies a predetermined direct voltage to the high-voltage site. A differential amplifier controls a current flowing through the transistor so that a potential difference generated between both ends of the third resistor becomes proportional to a potential difference generated between both ends of the current-detecting resistor. At this point, by measuring the voltage of a connection node of the first resistor and the second resistor, the value of a current flowing through the high-voltage site can be calculated from the measured value.
    Type: Application
    Filed: November 23, 2009
    Publication date: May 27, 2010
    Inventor: YUKIHIRA NAKAZATO
  • Publication number: 20100127719
    Abstract: The present invention relates to electromigration testing and evaluation methods and apparatus for a device under test with an interconnect structure. The method comprises forcing the occurrence of a step resistance-increase of the interconnect structure due to electromigration in the first layer and subsequently subjecting the interconnect structure to at least three respective predetermined stress conditions while concurrently measuring a test quantity indicative of an electrical resistance of the interconnect structure. The method allows performing an electromigration test in much shorter time than known electromigration testing methods, without loss of information or accuracy. It is therefore possible to accelerate the optimization of the interconnect manufacturing process so that the conductor electromigration kinetics remains compatible with a required product lifetime.
    Type: Application
    Filed: March 27, 2008
    Publication date: May 27, 2010
    Applicant: NXP, B.V.
    Inventor: Xavier Federspiel
  • Patent number: 7719293
    Abstract: Load current of a circuit is determined across a component of the circuit by calibrating the resistance of the component with a reference current having a distinguishable characteristic. For example, a reference current with swept frequency modulation is applied to the component so that the resistance of the component is determined from voltage drop associated with the reference current across the component. The component resistance is applied to a voltage drop associated with the load current to determine the load current. For example, a filter matched to the reference current frequency modulation isolates the reference current voltage drop so that a ratio of the reference current voltage drop and the load current voltage drop provides a ratio of the reference current and load current.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: May 18, 2010
    Assignee: Dell Products L.P.
    Inventor: Sandor Farkas
  • Patent number: 7719253
    Abstract: The present invention relates to system diagnostic circuitry for antenna systems with active antenna components. More specifically, the present invention discloses an apparatus comprising a connection between an antenna and a power supply conducting a first DC voltage, a source of a pulse width modulated signal, a lowpass filter for converting the pulse width modulated signal to a second DC voltage, and a comparator for comparing the first DC voltage and the second DC voltage and generating an output signal responsive to the difference between the first DC voltage and the second DC voltage.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 18, 2010
    Assignee: Thomson Licensing
    Inventors: John James Fitzpatrick, Robert Warren Schmidt, Robert Alan Pitsch, John Joseph Curtis, III
  • Patent number: 7710129
    Abstract: A potential measurement apparatus is provided which can suitably maintain the oscillation state of an oscillator including a detection electrode and stably measure the potential of a measurement object. The potential measurement apparatus includes a bearing part, an elastic supporting part supported by the bearing part, an oscillator movably supported by the elastic supporting part, detection electrodes installed in the oscillator, a drive mechanism driving the oscillator and a signal detection unit. The signal detection unit is connected to the detection electrodes to detect electrical signals appearing in the detected electrodes. A stress detecting element for generating an electric signal according to the stress of the elastic suspension part 142 is provided.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiyuki Ogawa, Yoshitaka Zaitsu, Takashi Ushijima, Atsushi Kandori, Kaoru Noguchi, Kazuhiko Kato, Futoshi Hirose
  • Publication number: 20100102836
    Abstract: An apparatus and method for determining a status of a power unit in a portable terminal are provided.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 29, 2010
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Jong-Su LEE, Youn-Lea KIM
  • Patent number: 7701230
    Abstract: One embodiment of the invention relates to an apparatus for profiling an ion beam. The apparatus includes a current measuring device having a measurement region, wherein a cross-sectional area of the ion beam enters the measurement region. The apparatus also includes a controller configured to periodically take beam current measurements of the ion beam and to determine a two dimensional profile of the ion beam by relating the beam current measurements to sub-regions within the current measuring device. Other apparatus and methods are also disclosed.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: April 20, 2010
    Assignee: Axcelis Technologies, Inc.
    Inventors: John Zheng Ye, Michael Paul Cristoforo, Yongzhang Huang, Michael A. Graf, Bo H. Vanderberg
  • Patent number: 7701226
    Abstract: Systems and methods for detecting the mode (a.k.a., state) of a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for determining three fuse states (uncut, cut, and destroyed) by comparing the fuse voltage with two reference voltages. Each fuse state has a different (indicative) impedance and is associated with a fuse voltage. The fuse voltage is below, between, or above two reference voltages, thereby determining the fuse state. One embodiment includes the fuse in series with a read transistor as well as two reference voltage generators, each comprising a resistor and a transistor (equivalent to the read transistor). Both resistors' impedances are greater than the uncut fuse impedance and one is less than the cut fuse impedance. Two comparators are used to bracket the fuse voltage, indicating that the fuse is uncut, cut, or destroyed.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: April 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaaki Kaneko
  • Patent number: 7696764
    Abstract: In some embodiments, the arrangement includes a sense element to convey a current from a source to a load and a compensation element located proximate to the sense element. The compensation element has a resistance that changes proportional to a change in temperature of the sense element. In several embodiments, the arrangement further includes an operational amplifier having a first input connected to the sense element, a second input connected to the compensation element and an output that provides an output signal that biases a current through the compensation element in response to a voltage across the sense element. In such embodiments, the bias current provides an output signal proportional to the conveyed current and the compensation element provides temperature compensation for the output signal. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventor: Viktor Vogman
  • Patent number: 7696765
    Abstract: A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.
    Type: Grant
    Filed: September 3, 2007
    Date of Patent: April 13, 2010
    Assignee: Broadcom Corporation
    Inventor: James Yu
  • Patent number: 7683796
    Abstract: An open-wire detection system and method includes a current transmitter that can be connected to one or more wires, wherein the current transmitter provides a minimum current and/or a current that is greater than the minimum current. An anti-aliasing filter is connected to an analog-to-digital converter, such that the anti-aliasing filter receives the minimum current provided by the current transmitter and provides an output signal to the analog-to-digital converter. A noise filter is generally connected to an open-wire threshold detector, wherein the noise filter and the open-wire threshold detector permit detection of input levels below the minimum current provided by the current transmitter. An output from the open-wire threshold detector can be sampled multiple times at intervals that correlate with a frequency of a plurality of digital signals to produce sampled data, such that if the sampled data is below the minimum current, one or more of the wires (e.g.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 23, 2010
    Assignee: Honeywell International Inc.
    Inventors: Benjamin J. Stad, Sudhir Thalore
  • Patent number: 7679380
    Abstract: The present invention discloses an overcurrent detection device, which uses a first NOT gate and a second NOT gate to reverse the logic states of a first digital signal and a second digital signal which are digitalized audio signals in a class D power amplifier. Next, a CMOS transistor receives the reversed digital signals and drives a load. A comparing circuit detects the current of the load and compares the current with the reversed first and second digital signals. When the current of the load is too high, the comparing circuit respectively outputs a first electrical signal and a second electrical signal to a first logic gate and a second logic gate. Then, the logic gate outputs a signal to activate a protection circuit to prevent the entire circuit be damaged or burned out.
    Type: Grant
    Filed: February 3, 2008
    Date of Patent: March 16, 2010
    Assignee: Tai-1 Microelectronics Corp.
    Inventor: Jy-Der David Tai
  • Publication number: 20100060302
    Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device includes a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.
    Type: Application
    Filed: September 28, 2009
    Publication date: March 11, 2010
    Inventor: Chang Soo JANG
  • Patent number: 7675298
    Abstract: Characteristics of a fluid are determined, in one embodiment, by flowing the fluid (which may contain charged particles) between a plurality of electrode pairs, applying respective DC voltages across at least two of the electrode pairs, and measuring resulting currents through the fluid at the respective electrode pairs. In one example, respective plates of the electrode pairs are configured so that they do not fully encircle one another.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: March 9, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Peter Forgacs
  • Patent number: 7675299
    Abstract: According to some embodiments, a method of determining a resistance of probes on a contactor device is disclosed. The contactor device can include a plurality of probes disposed to contact an electronic device to be tested. The method can include electrically connecting a pair of the probes to each other, and then forcing one of a voltage onto or a current through the pair of the probes. At a location on the contactor device, the other of a voltage across or a current through the pair of the probes can be sensed. A determination relating to a resistance of the probes can be determined from the values of the forced voltage or current and sensed other of the voltage or current.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: March 9, 2010
    Assignee: FormFactor, Inc.
    Inventor: Frederick J. Lane
  • Patent number: 7667470
    Abstract: A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Louis B. Capps, Jr., Glenn G. Daves, Anand Haridass, Ronald E. Newhart, Michael J. Shapiro
  • Publication number: 20100042389
    Abstract: Techniques and apparatus inhibit, limit, or remove biofouling and certain inorganic accumulations, to increase the longevity of accurate in-situ oceanographic and other underwater measurements and transducing processes. The invention deters formation of an initial bacterial layer and other precipitation, without harming the environment. The invention integrates an ultrasonic source into a sensor or other device, or its supporting structures. The ultrasonic source vibrates one or more critical surfaces of the device at a frequency and amplitude that dislodge early accumulations, thus preventing the rest of the fouling sequence. The ultrasonic driver is activated for short periods and low duty cycles, and in some cases preferably while the device is not operating.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Inventors: Guy J. Farruggia, Allan B. Fraser, John Hudak
  • Publication number: 20100042335
    Abstract: The invention relates particularly to methods and apparatuses for characterizing water-in-oil or invert emulsion fluids for use in drilling well bores in hydro-carbon bearing subterranean formations. A fluid stability measurement method is described. The method includes placing a sample of an emulsion in a gap between electrodes, disturbing the sample, measuring the electrical stability of the sample, and establishing a relationship between electrical stability and time since the sample was disturbed.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Inventor: Robert Murphy