Abstract: The present invention discloses a circuit lifetime measuring device to estimate the rest lifetime of a target circuit, comprising: a reference clock receiving end for receiving a reference clock; a correlation signal generating circuit for providing a correlation signal in which at least some operating settings of the correlation signal generating circuit and the target circuit vary synchronously; a storage circuit for storing an initial relation between the reference clock and the correlation signal; a measuring circuit, coupled to the reference clock receiving end and the correlation signal generating circuit, for measuring a present relation between the reference clock and the correlation signal; and an estimating circuit, coupled to the storage circuit and the measuring circuit, for generating an estimation value according to the initial relation and the present relation, wherein the estimation value indicates the rest lifetime of the target circuit.

Abstract: Disclosed is a signal transmission circuit device (200) including a feedback signal transmission unit (210) that feeds back a control output signal (Sout) as a feedback signal (Sf) to an input side circuit (200A). A logical comparison circuit (212) detects “mismatch” between input and output by performing logical comparison between a control input signal (Sin) and the feedback signal (Sf). When a state of “mismatch” between input and output occurs, a first pulse generating circuit (202) or a second pulse generating circuit (204) outputs a first correction signal (Sa1) or a second correction signal (Sa2) corresponding to a potential (high level or low level) of the control input signal (Sin), and corrects the control output signal (Sout) to the same potential (high level or low level) as the control input signal (Sin). With such configuration, the mismatch between input and output can be automatically corrected.

Abstract: In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.

Abstract: A semiconductor device includes a through silicon via (TSV) formed in a semiconductor substrate including a first-type impurity; and a first doping region formed in the semiconductor substrate located below the TSV. The first doping region is configured to include a second-type impurity and selectively electrically coupled to the TSV.

Abstract: The present invention proposes a testing method for testing a semiconductor element, including: providing a semiconductor element having a first surface on which a first testing area is formed and a second surface on which a second testing surface is formed; placing the semiconductor element on a plane surface, allowing any one of the first surface and the second surface to be in no parallel to the plane surface; and electrically connecting a testing apparatus to the first testing area and the second testing area of the semiconductor element. The semiconductor element is placed in a non-horizontal manner on the testing apparatus, which makes contact with the two opposing surfaces of the semiconductor element in a horizontal way without directly exerting a downward force against the surface of the semiconductor element, thereby preventing the semiconductor element from damages.

Abstract: A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.

Abstract: In accordance with an embodiment, a method of testing a power supply controller includes detecting whether an external switch is coupled between a first supply pin and the second supply pin. If the external switch is detected, the method determines whether there is a short circuit between the second supply pin and the switching output pin. If the short circuit between the second supply pin and the switching output pin is not detected, however, the method determines whether there is a short circuit between a switch control pin and the second supply pin. If the short circuit between the switch control pin and the second supply pin is not detected, the method determines whether there is a conductive path between the first supply pin and the second supply pin when the switch control pin activates the external switch.

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in ac

Abstract: Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.

Abstract: A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.

Abstract: A liquid crystal display (LCD) includes a pixel unit having pixels, each of the pixels positioned at a corresponding intersection of gate lines and data lines. A drive circuit unit is positioned at one side of the pixel unit to supply driving signals to the gate lines and the data lines. Test pads are connected to the data lines. In the LCD, each of the data lines is electrically connected between the pixel unit and the drive circuit unit via one or more lines among a first line formed in a first layer and a second line formed in a second layer, and wherein each of the data lines is connected to a different test pad from the test pad connected to adjacent data lines in each of the first and second layers.

Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.

Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Abstract: In accordance with an embodiment, an integrated circuit includes a plurality of devices on the integrated circuit. Each device includes a driving circuit, an individual contact pad coupled to a first terminal of the driving circuit, and a switch having a first terminal coupled to the first terminal of the driving circuit. Also, the integrated circuit includes a shared contact pad coupled to a second terminal of each switch of the plurality of devices. The integrated circuit also includes a controller coupled to each switch of the plurality of devices, where the controller is configured to selectively control each switch to couple each driving circuit to the shared contact pad.

Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.

Abstract: Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens positioned in front of the laser to focus the laser beam on an active region of an integrated circuit through a back side of an integrated circuit die, and a detector positioned to receive a reflected laser beam reflected from the active region through a back side of the die, through the objective lens. The detector is configured to detect an amplitude modulation of the reflected laser beam wherein the amplitude modulation is attributable to the electric field at the active region.

Abstract: A potential of a gate of the transistor of the memory cell is held at a predetermined potential VGM which is between a potential VGL used in normal holding and a threshold of the transistor Vth. When the potential is held for a predetermined period, the memory cell becomes in a similar state in which the memory cell is held at a potential VGL in 10 years. A memory cell, which does not hold data sufficiently at this time, can be judged not to hold data for 10 years in normal use.

Abstract: A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.

Abstract: Provided are a tester configured to test a semiconductor device and a test system including the same. The tester may include at least one contact unit and at least one memory controller. The contact unit is in contact with the semiconductor device. The memory controller is connected to the contact unit. The memory controller controls data input/output (I/O) operations of the semiconductor device and tests the semiconductor device.

Abstract: In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage.

Abstract: A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided.

Abstract: A device for monitoring operating parameters of integrated circuits. A signal is generated at least at one output of a comparison element by comparing switching states of input signals at the at least two inputs of the comparison element, which signal indicates that the at least one operating parameter has fallen below or has exceeded a predefined threshold. The two input signals are generated by at least two operating parameter-dependent devices, and the switching behavior thereof is subject to a time delay depending on the current value of the at least one operating parameter. A predefined time delay has a value such that when the predefined threshold of the operating parameter is exceeded, one of the input signals changes its switching state at the times predefined for the comparison element by the clock signal on the basis of the time delay.

Abstract: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.

Abstract: A method is described for accurate measuring of the excess carrier lifetime on a semiconductor sample from the carrier decay after termination of the excitation pulse imposed on the steady-state carrier excitation. The method includes determining a quality of decay parameter using progressing segments in each carrier decay; establishing an accurate lifetime measurement multiparameter domain for experimental variables whereby the quality of decay parameter falls within prescribed limits from the ideal exponential decay value of QD=1; and determining an excess carrier lifetime for the semiconductor sample based on experimental measurement conditions within the domain and the quality of decay value within the predetermined range indicative of an accurate excess carrier lifetime measurement.

Abstract: A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having a main current flowing therethrough, the termination structure surrounding the cell structure, the method includes a first test step of testing dielectric strength of the semiconductor device, a charge removal step of, after the first test step, removing charge from a top surface layer of the termination structure, the top surface layer being located on the substrate and formed of an insulating film or a semi-insulating film, and a second test step of, after the charge removal step, testing dielectric strength of the semiconductor device.

Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Abstract: A method of obtaining an electrical property of a test sample, comprising a non-conductive area and a conductive or semi-conductive test area, by performing multiple measurements using a multi-point probe. The method comprising the steps of providing a magnetic field having field lines passing perpendicularly through the test area, bringing the probe into a first position on the test area, the conductive tips of the probe being in contact with the test area, determining a position for each tip relative to the boundary between the non-conductive area and the test area, determining distances between each tip, selecting one tip to be a current source positioned between conductive tips being used for determining a voltage in the test sample, performing a first measurement, moving the probe and performing a second measurement, calculating on the basis of the first and second measurement the electrical property of the test area.

Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.

Abstract: There is provided a test apparatus for testing a device under test, including a test signal generator that generates a test signal to test the device under test, an electric-photo converter that converts the test signal into an optical test signal, an optical interface that (i) transmits the optical test signal generated by the electric-photo converter to an optical receiver of the device under test and (ii) receives and outputs an optical response signal output from the device under test, a photo-electric converter that converts the optical response signal output from the optical interface into an electrical response signal and transmits the electrical response signal, and a signal receiver that receives the response signal transmitted from the photo-electric converter and a test method.

Abstract: Embodiments include a testing arrangement for testing a first package, the testing arrangement comprising a frame having a top section and a bottom section, wherein the bottom section of the frame comprises a pickup section, and wherein the pickup section has a first air pathway; a second package mounted on a top surface of the bottom section of the frame such that a second air pathway is defined between (i) the second package and (ii) the top surface of the bottom section of the frame; and a vacuum path defined by (i) the first air pathway and (ii) the second air pathway, wherein during testing of the first package, a vacuum in the vacuum path is generated such that the pickup section of the bottom section of the frame holds the first package.

Abstract: A method and circuit for implementing high current capability Kelvin connections and measuring the resistance of the contacts and connections to verify that the conducting path is capable of carrying the high current without damage or degraded performance. Included as well is the means and circuit for efficiently dividing a high current test stimulus current into 2 paths with low losses and voltage drops.

Abstract: Circuits for performing four terminal measurement point (IMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: A system and a method are disclosed for testing thru-silicon vias (TSVs) in a silicon die. A silicon die containing multiple TSVs is mounted on a wafer tape. Two probe points are probed on the exposed side of the silicon die. A resistance is measured between the two probe points and an electrical integrity is determined based on the measured resistance.

Abstract: Techniques for testing an electronic device with through-device vias can include using a probe card assembly with probes for contacting connection structures of the electronic device including ends of through-device vias of the electronic device. A pair of the probes can be electrically connected in the probe card assembly and can thus contact and form a direct return loop from one through-device via to another through-device via of a pair of the through-device vias with which the pair of probes is in contact. The electronic device can include test circuitry for driving a test signal onto the one of the through-device vias and a receiver for detecting the test signal on the other of the through-device vias.

Abstract: A system for measuring soft starter current includes a current monitoring system including a controller and a current transfer device that includes a first thyristor and a first conductor coupled to the first thyristor and configured to convey a first current flowing through the first thyristor, wherein the first current includes current flowing through the first thyristor when the first thyristor is in an off state. The system also includes a first current sensor configured to sense the first current and a first current measurement circuit coupled to the first current sensor and coupleable to the controller and configured to output a first output value to the controller representative of the first current flowing through the first thyristor. The controller is configured to determine an impending inoperability of the first thyristor based on the first current and alert a user if the first current indicates the impending inoperability.

Abstract: A light emitting device control circuit controls a light emitting array which includes a plurality of light emitting device strings. Each light emitting device string includes a first terminal which is connected to a common node, a second terminal, and a plurality of light emitting devices connected in series. The light emitting device control circuit includes: a short detection circuit, coupled to the second terminals to receive second terminal signals from the second terminals, generating comparison signals according to whether the second terminal signals are higher than a reference signal, and generating a short detection signal according to whether a number of the comparison signals is between a first setting value and a second setting value.

Abstract: A method for characterizing the electronic properties of a semiconductor sample by exploiting transients in measured photoconductance, the transients being induced by illuminating the semiconductor sample with a small probing illumination that is superimposed over a larger background illumination. In one embodiment, a pulse-type probing illumination is utilized, with either the intensity of the probing illumination being gradually reduced or the intensity of the background illumination being gradually increased until the measured photoconductance rise and decay in the sample are substantially exponential. In another embodiment, a continuous probing illumination with a sinusoidally-modulated intensity is utilized, the modulated intensity of the probing illumination being gradually adjusted until the measured photoconductance is linearly dependent thereupon.

Abstract: A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

Abstract: A semiconductor device includes a base film, a semiconductor chip mounted on the base film, and a plurality of leads formed on the base film, each of the leads including one end coupled to the semiconductor chip and another end being opposite to the one end. The another end of a first one of the leads and the another end of a second one of the leads are located at different positions respectively between the semiconductor chip and a cut line along which the base film is cut.

Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.

Abstract: Methods, systems, and apparatus for testing semiconductor devices.

Abstract: The present invention provides devices and methods for testing the electrical performance of thin-film transistor backplane arrays and protecting thin-films during testing and handling.

Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.

Abstract: Mechanisms are provided for chip (e.g., semiconductor chip) identification (e.g., low cost secure identification). In one example, a method of manufacturing for implementing integrated chip identification is provided. In another example, a method of using a chip with an integrated identification is provided.