Abstract: An electronic device has terminals for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver and a terminal control circuit for receiving a terminal configuration defining the properties and multiplexing of the terminal. The actual configuration of the terminal driver is set according to the terminal configuration. The device has at least one terminal checker arranged for comparing the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed, and for, when said comparing indicates a not allowed configuration, setting the actual configuration to a default configuration. Advantageously safe operation of the device in a system is achieved by monitoring the configuration of the multiplexed terminals, and switching to a default configuration when in error.

Abstract: An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.

Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.

Abstract: A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

Abstract: An apparatus, system and method are disclosed to block and replace intermediate combinatorial transitions that are correlated with secret data, also referred to as glitches, with random intermediate combinatorial transitions that are uncorrelated with the data being processed.

Abstract: In some embodiments, a circuit may include a configurable logic module including a multiplexer. The multiplexer may include a plurality of data inputs configured to receive one or more bit strings. Each of the one or more bit strings may correspond to a logic operation. The multiplexer may further include a first control input configured to receive a first input signal, a second control input configured to receive a second input signal, and an output configured to provide an output signal corresponding to a selected logic operation based on the first input signal and the second input signal.

Abstract: An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.

Abstract: A netlist converter, which generates configuration information for reconfiguring a reconfigurable logic operation unit, includes: a mapping unit that enumerates k-feasible cuts where the number of nodes after cutting is an integer k or fewer, out of all cuts for each node included in a netlist generated based on a specification to be processed in the logic operation unit; and a generating unit that generates configuration information including element reconfiguration information that reconfigures elements by selecting cuts assigned to the elements out of the enumerated k-feasible cuts and channel reconfiguration information for reconfiguring the data transfer channels to realize the netlist by connecting the reconfigured elements.

Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

Abstract: A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.

Abstract: An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.

Abstract: A circuit includes a power amplifier that includes a transformer having a primary winding and a secondary winding. The secondary winding has a first terminal and a second terminal. The circuit also includes a transmit/receive switch electrically connected between the first terminal of the secondary winding and electrical ground. The second terminal of the secondary winding is electrically connected to an antenna that transmits signals based on an output of the power amplifier and to an input of a second amplifier that is also connected to the antenna. The transmit/receive switch selectively switches between a closed position that connects the secondary winding to ground in a transmit mode and an open position that disconnects the secondary winding from ground in a receive mode.

Abstract: A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.

Abstract: The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer readable instructions, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a negative pulse generator which is adapted to reduce the charge on capacitor in one or more volatile memory cells to zero logic by using a switch connected to the Voltage Reference (Vref) of the volatile memory cell, a controller and a negative power supply. The switch and the negative power supply impose a negative pulse on the Vref of the volatile memory cells on being instructed by the controller at the occurrence of a predefined event. An erasure module associated with the controller is provided for instructing the erasure circuitry for erasing data at the occurrence of a predefined event.

Abstract: The present invention relates to the field of reconfigurable computing also known as dynamic computing and, more particularly, to reconfigurable architectures logic gates and programmable wiring connections between them and the input interfaces and output interfaces. There is growing interest in developing new hardware architectures to complement or replace existing static architectures, and recently, there has been a theoretical direction to explore the richness of nonlinear dynamical systems to implement reconfigurable hardware (dynamic). The present invention is to use a nonlinear to emulate different logic gates dynamic system that are the basis of general-purpose computing, and after obtaining the logic gates, integrate these elements into a programmable device by the user, ie for create a field programmable array of reconfigurable logic gates.

Abstract: The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: Described is an apparatus for generating a thermometer code, the apparatus comprises: a 2-bit bi-directional shift register; and more than two multiplexers operable to form storage units and coupled together in a chain to generate the thermometer code, the more than two multiplexers controlled by outputs of the 2-bit bi-directional shift register.

Abstract: An apparatus includes a semiconductor fuse array, disposed on a semiconductor die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored.

Abstract: An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

Abstract: An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.

Abstract: An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

Abstract: An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract: An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

Abstract: Global optimization and verification of cyber-physical systems using graphical floating point math functionality on a heterogeneous hardware system (HHS). A program includes floating point implementations of a control program (CP), model of a physical system (MPS), objective function, requirements verification program (RVP), and/or global optimizer. A simulation simulates HHS implementation of the program using co-simulation with a trusted model, including simulating behavior and timing of distributed execution of the program on the HHS, and may verify the HHS implementation using the RVP. The HHS is configured to execute the CP and MPS concurrently in a distributed manner. After deploying the program to the HHS, the HHS is configured to globally optimize (improve) the CP and MPS executing concurrently on the HHS via the global optimizer. The optimized MPS may be usable to construct the physical system. The optimized CP may be executable on the HHS to control the physical system.

Abstract: An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Abstract: This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.

Abstract: A jack detector detects a combination state between a socket including a detecting pin and a first signal pin and a jack. The jack detector includes a first current source for supplying a first detecting current, a second current source for supplying a second detecting current larger than the first detecting current, and a buffer for generating a detecting signal in accordance with a detecting pin voltage input from the detecting pin. The second current source instead of the first current source is connected to the detecting pin in synchronization with a combination starting point when the detecting pin and the first signal pin are electrically connected to each other and it is determined that the jack is combined with the socket when the detecting signal is maintained at a state of the combination starting point.

Abstract: An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals. The finite state machine frames the serialized virtual GPIO signals into frames each demarcated by a start bit and an end bit.

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract: Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate.

Abstract: A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit (IC) connected to components on a circuit board is described. The method includes processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components on the circuit board; displaying a graphic user interface (GUI) of the circuit design tool to connect a circuit board interface described in the first file with a circuit design interface in the circuit design; generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described as being connected to the selected circuit board interface; and generating a bitstream to configure the programmable IC. The bitstream includes a physical implementation of the circuit design satisfying the physical constraints.

Abstract: A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal.

Abstract: In a data processing system, a method for implementing a factor graph having variable nodes and function nodes connected to each other by edges includes implementing a first function node and a on a first computer system, the first computer system being in network communication with a second computer system; establishing a network connection to each of a plurality of processing systems; receiving, at the first function node, soft data from a variable node implemented on one of the processing systems, the soft data including an estimate of a value and information representative of an extent to which the estimate is believed to correspond to a correct value; and transmitting, from the first function node to the one of the processing systems, soft data representing an updated estimate of the value.

Abstract: A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

Abstract: A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Abstract: A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract: Various features pertain to circuit design schemes that route wires based on temperature. In one aspect, time-variant temperature conditions along a prospective route are taken into account when determining whether to use the route for a wire. For example, a route can be selected from among a set of prospective two-dimensional (2-D) or three-dimensional (3-D) routes based on which route is associated with the “smoothest” temperature gradient. Other aspects of the disclosure pertain to determining or exploiting adjustable search windows, layer wiring densities, worst-case skew values and resistance-capacitance (RC) coupling characteristics, particularly for use with 3-D routing within the layers of a stacked multi-layer substrate.

Abstract: A nonvolatile programmable logic switch of an embodiment includes: a cell including: a first memory including a first terminal connected to a first wiring line, and a second terminal; a second memory including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory; a first transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a third wiring line, and a gate is connected to a fourth wiring line; and a second transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a gate of a pass transistor, and a gate is connected to a fifth wiring line.

Abstract: A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.

Abstract: Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

Abstract: A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (MRS) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its upper layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.