Abstract: Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

Abstract: Method and apparatus for programmable heterogeneous integration of stacked semiconductor die are described. In some examples, a semiconductor device includes a first integrated circuit (IC) die including through-die vias (TDVs); a second IC die vertically stacked with the first IC die, the second IC die including inter-die contacts electrically coupled to the TDVs; the first IC die including heterogeneous power supplies and a mask-programmable interconnect, the mask-programmable interconnect mask-programmed to electrically couple a plurality of the heterogeneous power supplies to the TDVs; and the second IC die including active circuitry, coupled to the inter-die contacts, configured to operate using the plurality of heterogeneous power supplies provided by the TDVs.

Abstract: To optimize the arrangement of configuration data stored in a configuration memory. A lookup table includes a memory configured to store configuration data, a plurality of multiplexers each configured to select one signal from a plurality of input signals in accordance with the configuration data supplied from the memory and output the one signal, and an inverter. The plurality of multiplexers are connected in a binary tree with multiple levels. The inverter is provided between one of input terminals of a multiplexer in an uppermost level and an output terminal of a multiplexer in one level lower than the uppermost level. Signal selection is performed in each of the multiplexers so that the multiplexer in the uppermost level outputs, as an output signal, one signal of all input signals of the multiplexers in a lowermost level.

Abstract: The disclosure provides a server including a baseboard management controller (BMC), a programmable logic device (PLD) and a blocking unit. The BMC receives an update instruction, and according to the update instruction, generates a firmware update data. The BMC generates an update signal according to on a reception state of the update instruction. The PLD is coupled to the BMC, receives the firmware update data to update a firmware. When the firmware is updated, the PLD generates a restart signal. The blocking unit is coupled to the BMC and the PLD, receives the update signal and the restart signal, and according to the update signal, determines whether to block the restart signal.

Abstract: A logic module includes a device for implementing a logic function the device including at least one input and at least one output, the output at least partially representing the result of the logic function; at least one first element including at least one resistance state, at least one second element formed by a bipolar resistive memory; the first element and the second element having a common electrode connected to the output.

Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Abstract: A digital input includes a galvanically isolated section having an integrating capacitor coupled to a high voltage signal input by at least one current-limiting resistor, a relaxation oscillator coupled across the integrating capacitor, and an electronic switch controlled by the relaxation oscillator. An optical isolator has an input side and an output side, wherein the input side is coupled across the integrating capacitor by the switch, and a low voltage section includes a decoder having an input coupled to the output side of the optical isolator and having a low voltage signal output.

Abstract: A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium.

Abstract: A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.

Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (MRS) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals.

Abstract: A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

Abstract: One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

Abstract: A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.

Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract: An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resistances being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of the external device in order to provide a calibration voltage. The comparing circuit compares the calibration voltage to a reference voltage and provides a code signal for calibrating the impedance corresponding to output data with the input/output impedance of the external device. The impedance calibration circuit calibrates an impedance mismatch between the impedance calibration circuit and a data input/output driver by adjusting the impedance of the impedance calibration circuit through the variable resistance.

Abstract: An electronic circuit in a package, including two functions, the package orientation activating a single one of the two functions.

Abstract: Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

Abstract: One embodiment of a nonvolatile logic circuit includes a logic circuit comprising a first source terminal, a second source terminal, at least one input terminal, and an output terminal to temporarily store a logic state with a power dependent status, a high voltage source coupled to the first source terminal, a low voltage source coupled to the second source terminal, an intermediate voltage source comprising an electrical potential higher than that of the low voltage source but lower than that of the high voltage source, and a nonvolatile reversible resistance element coupled to the output terminal at a first end and to the intermediate voltage source at a second end. The nonvolatile reversible resistance element preserves the logic state of the logic circuit which is controlled by an input signal applied to the at least one input terminal. Other embodiment are described and shown.

Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract: Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: A logic device is described. The logic device includes magnetic input/channel regions, magnetic sensor region(s), and sensor(s) coupled with the magnetic sensor region(s). Each magnetic input/channel region is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that domain wall(s) reside in the magnetic input/channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input/channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to the magnetic input region(s). The magnetic input/channel region(s) include FexCoyNizM1q1M2q2, with x+y+z+q1+q2=1, x, y, z, q1, q2 at least zero and M1 and M2 being nonmagnetic.

Abstract: One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

Abstract: A computing multi-magnet device and method for solving complex computational problems is provided. Embodiments include a first magnet, a second magnet, and an interconnect between and interconnecting the first and second magnets, the interconnect configured to allow the first and second magnets to communicate via a voltage or current applied to the first and second magnet and conducted by the interconnect. The scalability of computing multi-magnet device provides solutions to algorithms that have exponentially increasing complexity.

Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: A method for the design and manufacturing of a 3D semiconductor device including a first circuit stratum and a second circuit stratum, the method including: applying a synthesis tool with at least first and second technology libraries; and performing a synthesis that utilizes the at least first and second technology libraries, where the first and second technology libraries correspond to two different processes, where the first technology library targets the first circuit stratum and the second technology library targets the second circuit stratum, and where the performing a synthesis results in a netlist, the netlist includes first cells of the first technology library and second cells of the second technology library.

Abstract: A magnetic memory cell is provided that includes a free layer that is pinned on both of its sides to form one or more domain wall structures. The one or more domain wall structures define one or more logic states by controlling the motion of the one or more domain wall structures.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: A computing multi-magnet device and method for solving complex computational problems is provided. Embodiments include a first magnet, a second magnet, and an interconnect between and interconnecting the first and second magnets, the interconnect configured to allow the first and second magnets to communicate via a voltage or current applied to the first and second magnet and conducted by the interconnect. The scalability of computing multi-magnet device provides solutions to algorithms that have exponentially increasing complexity.

Abstract: An electromagnetic wave generator includes first and second electrodes facing each other and spaced apart from each other; a chargeable particle disposed between the first and second electrodes; a voltage source which applies a voltage between the first and second electrodes; and an antenna electrically connected to one of the first and second electrodes and which radiates an electromagnetic wave due to induced current oscillation based on the applied voltage.

Abstract: Consistent with embodiments of the present disclosure a redriver circuit is provided for a first and a second serial-unidirectional communications channel. The redriver circuit conditions received data signals by adjusting signal properties to correct for signal level attenuation and noise. The conditioned data signals are transmitted to corresponding outputs of the channels. The redriver circuit disables, in response to a first enable signal being inactive, current drawing circuitry of components for both channels on a common side of the redriver. The redriver circuit disables, in response to a second enable signal being inactive, current drawing circuitry of components for both channels on the other side of the redriver.

Abstract: An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.

Abstract: An embodiment of a technique to capture and locally synchronize data is disclosed. The technique includes receiving first and second signals through a first interface, and receiving a third signal through a second interface where the third signal is unsynchronized with respect to the second signal. The technique further includes detecting a first phase difference between the second and third signals, and generating a fourth signal in a manner so that a second phase difference between the fourth signal and one of the second or third signals is a function of the first phase difference. In addition, the technique includes storing a state of the first signal in response to the fourth signal, and thereafter supplying the stored state of the first signal to the second interface.

Abstract: A dynamically reconfigurable linear core logic gate is a device that allows logical outputs dependent upon configurable parameters set within device. The device is comprised of three blocks: The first block receives at least one input signal and determines whether the signal or signals are low or high in comparison with a threshold reference signal. The second block sums the logic signals of the first block with an offset signal. The third block determines if the sum realized in the second block is a low or high by checking whether the sum falls within a predetermined interval.

Abstract: A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.

Abstract: A system provides for the distribution of intellectual property logic blocks from a source to a user wherein the user may use the logic blocks during development but is prevented from using the block in production without permission. A sensor is connected in parallel with a first signal from the block and in series with a second signal from the block. When activity on the first signal exceeds a predetermined count, the output of the second signal is corrupted. In some embodiments all such sensors are connected to an aggregator which allows all blocks to continue to operate until all of them have exceeded their predetermined activity count. A state machine compares the values of two keys, one stored within the block, to another value stored in the state machine controller, and allows the block to be used in production if the key values coincide.