Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.

Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

Abstract: Aspects of the disclosure are directed to a voltage level shifter architecture, including a voltage level shifter with circuitry residing within a footprint; and an internal augmented voltage generator residing within the footprint, wherein the internal augmented voltage generator is coupled to the voltage level shifter to augment a voltage level shift.

Abstract: A trigger, includes: a first voltage input terminal; a bias voltage input terminal; a first bias transistor having a scaling of N to a first component of an external device; a comparator transistor having a scaling of N to a second component of the external device; a first switch transistor and a second switch transistor; a shunt transistor having a control terminal connected to the first voltage input terminal, a second terminal connected to the second terminal of the second switch transistor, and a first terminal connected to the first terminal of the comparator transistor. The shunt transistor has an enlarging scale of M to the comparator transistor. A voltage output terminal is respectively connected to the second terminal of the first switch transistor, the control terminal of the second switch transistor, and the second terminal of the comparator transistor.

Abstract: This invention provides an array-type processing device which can reduce power consumption and can also reduce a processing performance drop caused by switching of configuration information. An array-type processing device, which includes a first domain and a second domain, the device comprises a plurality of processing units which are allocated in the first domain, and each of which includes a plurality of processing elements and a router configured to control connections between the plurality of processing elements, a configuration information supply unit configured to supply configuration information to one or more processing units of the plurality of processing units, the configuration information supply unit being allocated in the second domain, and a power supply control unit configured to control the power supply to the plurality of processing units, the power supply control unit being allocated in the second domain.

Abstract: A master electronic device used to perform communication with a slave electronic device is provided. The master electronic device includes a power module, an input and output (I/O) module, a processing module, a sample and hold module and a control module. The power module outputs power having a default operation voltage. The I/O module operates according to the power having the default operation voltage. The processing module controls the I/O module to generate and transmit a command signal to the slave electronic device. The sample and hold module receives and samples a response signal from the slave electronic device. The control module determines a slave operation voltage according to a high state voltage level of the response signal, so as to further control the power module to generate power having the slave operation voltage such that the I/O module operates accordingly.

Abstract: An object information acquiring apparatus includes a detector including m-number of probes to which a voltage is supplied and a current/voltage conversion circuit which converts a current into a voltage, a receiver processing electric signals from the probes, and a relay board respectively relaying power distribution lines between the electrical power source and the probes and signal wirings between the receiver and the probe, wherein the relay board receives input of signal wirings and power distribution lines from n-number (m?n) of probes among the m-number of probes, connects the signal wirings from the n-number of probes to the receiver, and connects, to the electrical power source side, the power distribution lines of a number that is fewer than the power distribution lines from the n-number of probes.

Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

Abstract: To realize a level shift circuit with the small occupation area and capable of performing high-speed operation, a level shift circuit includes an electric potential converting unit that converts a first electric potential of an input signal to a third electric potential and converts a second electric potential of an input signal to a fourth electric potential. A capacitor includes first and second electrodes, the first electrode being electrically connected to the input unit, and the second electrode being electrically connected to an output node of the electric potential converting unit. A buffer unit converts the third and fourth electrical potentials to fifth and sixth electrical potentials, respectively. The capacitor reflects the input signal in the electric potential of the output node of the electric potential converting unit without delay by capacitive coupling, thereby realizing a level shift circuit that is capable of performing high-speed operation.

Abstract: A circuit is disclosed that includes a first switch unit, a first level shift unit and a second level shift unit. The first switch unit is configured to receive a first dynamic input voltage, and to generate a first operation voltage at a first operation terminal or generate a second operation voltage at a second operation terminal according to the first dynamic input voltage. The first level shift unit is coupled to the first switch unit at the first operation terminal, and is configured to shift the first operation voltage to a first output voltage having a first level at an output terminal according to a first supply voltage. The second level shift unit is coupled to the first switch unit at the second operation terminal, and is configured to shift the second operation voltage to the first output voltage having a second level according to a second supply voltage.

Abstract: Methods and systems are described for emulating a bi-directional synchronous communications protocol for bi-directional bus communication using unidirectional channels between a master device and a slave device. The master device includes a physical interface to the unidirectional channels that resynchronizes outgoing and incoming data streams in order to reconstruct a bitstream that is compliant with the bi-directional synchronous communications protocol. The reconstructed bitstream is input to the master digital interface controller as though it had been received from the slave device.

Abstract: Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.

Abstract: A power supply voltage switching circuit includes a power selecting module, a level shifting module, and a supply switching module. The power selecting module receives a first supply signal and a second supply signal, and outputs an intermediate supply signal according to the first supply signal and the second supply signal. The level shifting module receives the intermediate supply signal as a power supply, and generates a first shifted signal and a second shifted signal by shifting voltage levels of a first control signal and a second control signal respectively. The supply switching module receives the first supply signal and a third supply signal, and generates an output signal according to the first shifted signal, the second shifted signal, the first control signal, and the second control signal.

Abstract: An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level.

Abstract: A semiconductor arrangement (10) with an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor arrangement (10) comprises a first semiconductor chip (20a) with a first integrated circuit (25a) and a second semiconductor chip (20b) with a second integrated circuit (25b). The semiconductor arrangement has an ESD protection circuit (30). The first semiconductor chip (20a) is isolated otherwise form the second semiconductor chip (20b) and the first integrated circuit (25a) is connected to the second integrated circuit (25b) exclusively via the ESD protection circuit (30).

Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.

Abstract: A semiconductor structure is provided. A first conductive layer is formed between a substrate and a first insulating layer. A semiconductor layer is disposed over the first insulating layer. A second conductive layer is formed between a semiconductor layer and a second insulating layer and includes a first segment and a second segment. A third conductive layer is disposed over the second insulating layer. The first insulating layer, the semiconductor layer, the first segment and the second segment constitute a first transistor. The third conductive layer, the semiconductor layer, the first segment and the second segment constitute a second transistor. During a first period, the first and third conductive layers receive a first voltage level and a second voltage level respectively. During a second period, the first and third conductive layers receive a third voltage level and a fourth voltage level respectively.

Abstract: Example apparatus for power-domain assignment, having: a first bus-to-switch interface; a second bus-to-switch interface; a first power-domain bus, coupled to the first bus-to-switch interface; a second power-domain bus, coupled to the second bus-to-switch interface. A set of I/O signal level shifters, coupled between the first and second power-domain buses; a switch including, a set of IP block power coupling outputs; a set of IP block I/O signal paths; and a selection signal input. The switch is coupled to the first and second bus-to-switch interfaces. Wherein, in response to receiving a first signal on the selection signal input, the switch is configure to couple the first power-domain bus to the set of IP block power coupling outputs; and wherein, in response to receiving a second signal on the selection signal input, the switch is configure to couple the second power-domain bus to the set of IP block power coupling outputs.

Abstract: A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

Abstract: A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reducing power consumption. Recent energy performance requirements are causing the next-generation system manufacturers to explore approaches to lower power consumption. Subthreshold operation has been examined and implemented in designing ultra-low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the subthreshold regime, where the supply voltage used in operation is orders of magnitude below the normal operating voltage of typical transistors, has proven to be very beneficial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Circuits (ASICs).

Abstract: The present invention discloses an interface sharing apparatus and method, and a mobile communications terminal. The apparatus includes a control unit, a video processing unit, a switch unit, a detection control unit and a multiplexing interface. The detection control unit is configured to detect a first voltage from the multiplexing interface, and to compare the first voltage with a preset voltage value. If the first voltage is greater than zero and less than or equal to the preset voltage value, the detection control unit controls the switch unit, so that the video processing unit is connected to the multiplexing interface by using the switch unit. If the first voltage is equal to zero or greater than the preset voltage value, the detection control unit controls the switch unit, so that the control unit is connected to the multiplexing interface by using the switch unit.

Abstract: A galvanically isolated switch system and method comprising a plurality of switches having at least one terminal in series electrical connection, at least one control input electrically connected to at least one of the plurality of switches, wherein the at least one control input is isolated from direct current voltages and at least one passive component connected across the plurality of switches.

Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage.

Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

Abstract: A level conversion circuit includes level conversion portions which are connected in series. The level conversion portion includes circuit blocks. The circuit block inverts an input signal. The circuit block includes a transistor connected between a power supply and a node, a transistor connected between the node and a power supply, a transistor connected between a gate of the transistor and the power supply, and a capacitor connected between an output node and the gate of the transistor. The circuit block carried out level conversion in step with operation of the transistor in accordance with a signal applied from an input node to a gate thereof and operation of the transistor an ON/OFF state of which is switched by application of an output of the circuit block to a gate thereof, to thereby output potential change at the node.

Abstract: A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level. In one example, the total number of the transistors needed by the level shifter is much fewer than that of the prior art, and additional voltage sources are not needed to provide middle voltages. The manufacturing cost of the exemplary level shifter can be reduced and the signal level shifting efficiency of multi-power domain can be enhanced.

Abstract: A flying cap, level shifter has a capacitor with an upper plate connected to (i) a hybrid power supply (VDDH-VDDL) by an n-type transistor and (ii) a relatively high-voltage power supply VDDH by a p-type transistor. Both of the transistors are controlled by a voltage at the level shifter's output node, which is driven to either VDDH or ground. As such, one of the two transistors will always be on, such that the flying capacitor will be continuously recharged to a voltage difference that ensures that the level shifter will operate properly.

Abstract: A post driver comprises a source follower and a first sub-unit. The source follower includes an input to receive a first voltage from a pad, and an output to provide a second voltage. The first sub-unit includes a first transistor and a second transistor. The first transistor is coupled between the pad and a first power rail, and is configured to operate in a sub-threshold region in response to the second voltage and a first range of the first voltage. The second transistor is coupled in parallel with the first transistor between the pad and the first power rail, and is configured to electrically connect the pad to the first power rail in response to a second range of the first voltage.

Abstract: An integrated circuit has registers which it can place in a low power condition in which their state is lost; a power domain capable of reading the registers, the current operating mode of the domain being dependent on the state of the registers; a memory; and a configuration controller for configuring the registers. The configuration controller has access to a set of mappings. Each mapping indicates for bits represented in the memory the state of other bits storable in the registers. The configuration controller is configured to perform a register configuration operation by reading bits from the memory and populating the registers with a corresponding bit state.

Abstract: An emitter-coupled spin-transistor includes an emitter, a collector and a base. A first control wire receives an input current to create a magnetic field that affects amplification of the spin-transistor. A second transistor also includes an emitter, a collector and a base, where the emitter of the second transistor is coupled to the emitter of the spin-transistor to provide a logic circuit.

Abstract: Interface systems and methods are provided. An interface system can include a first isolator (200) and a second isolator (300) coupled to a modular interface (110). The interface can include a plurality of conductors (120). The first isolator can be coupled to a first signal format compliant first input/output (I/O) device (130). The second isolator can be coupled to a second signal format compliant second I/O device (140). The first isolator can pass a first signal format compliant signal to, and suppress the reflection of at least a portion of a second signal format compliant signal from, the first I/O device. The second isolator can at least partially block a first signal format compliant signal from, and to pass a second signal format compliant signal to, the second I/O device.

Abstract: An A/D conversion circuit and a solid-state imaging device are able to reduce current consumption, and two input terminals of a NAND element included in a latch circuit receive a corresponding one of a plurality of clock signals and an enable signal. The enable signal is not input to the NAND element before an end timing of A/D conversion, and is input to the NAND element at the end timing of the A/D conversion and at a timing at which latching is performed. The latch circuit latches no clock signal when the enable signal is not input.

Abstract: An apparatus includes an integrated circuit (IC) adapted to be powered by a positive supply voltage. The IC includes a charge pump that is adapted to convert the positive supply voltage of the IC to a negative bias voltage. The IC further includes a bidirectional interface circuit. The bidirectional interface circuit includes an amplifier coupled to the negative bias voltage to accommodate a bidirectional input voltage of the IC. The bidirectional interface circuit further includes a comparator coupled to the negative bias voltage to accommodate the bidirectional input voltage of the IC.

Abstract: A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.

Abstract: A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.

Abstract: An I/O device comprises a driving unit coupled between a first voltage and a second voltage, and configured to receive a first signal so as to drive a second signal for swing with a second swing range narrower than a first swing range between the first voltage and the second voltage and supply the second signal to a transmission line. The driving unit includes a first stabilizer coupled between the first voltage and the transmission line and a second stabilizer coupled between the second voltage and the transmission line.

Abstract: A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively. The gate terminals of the third and fourth switching elements are connected to the rise detector circuits, and the third and fourth switching elements are turned on by the first and second output signals respectively.

Abstract: A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage.

Abstract: A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

Abstract: A level shifter circuit, wherein a first and a second transistor circuit are connected serially, a third and a fourth transistor circuit are connected serially; a first input voltage is applied to the second transistor circuit and a second input voltage is applied to the fourth transistor circuit; an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits; two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and the level shifter circuit has a switch element for applying a voltage to a common connection node.

Abstract: The invention provides a bidirectional level shifter which includes: a first signal terminal; a second signal terminal; a first switch, coupled between the first signal terminal and ground; an inverter receiving a signal from the first signal terminal; a Schottky diode including an anode and a cathode, the anode receiving a signal from the second signal terminal; a second switch, coupled between the cathode of the Schottky diode and the ground; a comparing circuit, comparing a reference voltage and a voltage at the second signal terminal to control the first switch, wherein the reference voltage is lower than a forward bias voltage of the Schottky diode; a first voltage source coupled to the first common node; and a second voltage source coupled to the second common node.

Abstract: A power supply switch circuit according to an aspect of the present invention includes a first switch element that is connected between a first power supply line and a second power supply line and switches connection and disconnection between the first power supply line and the second power supply line according to a first enable signal; a second switch element that is connected between the first power supply line and the second power supply line and switches connection and disconnection between the first power supply line and the second power supply line; and a switch control circuit that includes at least one logic gate supplied with power from the second power supply line and controls the second switch element. The switch control circuit controls the second switch element based on a second enable signal supplied to the switch control circuit and on a voltage of the second power supply line.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A level shifting device is disclosed. The device includes an input unit, a control unit, a high level generating unit, a low level generating unit and an output unit. The input unit generates a level selection signal and a plurality of output selection signals by sampling serial input data. The control unit selectively generates a high level activation signal or a low level activation signal based on the input data, and generates a switching signal based on the input data. The high level generating unit generates a high level output signal in response to the high level activation signal, and the low level generating unit generates a low level output signal in response to the low level activation signal. The output unit outputs one of the high level output signal and the low level output signal to each of a plurality of output signals in response to the switching signal.

Abstract: Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.

Abstract: In various embodiments, a reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.

Abstract: The present invention provides a level translator circuit, a driving circuit for driving a high-voltage device and a corresponding method. The driving circuit for driving a high-voltage device comprises: a zener diode whose cathode is connected to a high-voltage power supply voltage and whose anode is connected to a ground potential of a low-voltage domain through a resistor; a high-voltage PMOS transistor whose gate is connected to an anode of the resistor, whose drain is connected to the ground potential of the low-voltage domain, and whose source is operable to supply a ground potential of a high-voltage domain; a level translator operable to convert a first signal in the low-voltage domain as received to a second signal in the high-voltage domain and output the second signal; and a low-voltage driving circuit operable to receive the second signal and adapt the second signal as a third signal which can drive the high-voltage device.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.

Abstract: In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed.