Abstract: Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.

Abstract: Apparatus and methods are disclosed, such as those involving data transmission. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the pair of switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel, and a second node. The receiver also includes a resistance generating a voltage drop between the first node and the second node. The receiver further includes a first transistor of a first type and a second transistor of a second type. The first and second transistors are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference.

Abstract: An output circuit includes a first differential pair of transistors driven by a first current source and differentially receiving input signals and a second differential pair of transistors driven by a second current source and differentially receiving first control signals (EMT, EMB). Output pairs of the first and second differential pairs are connected to the differential output terminals. A load resistor element pair is connected between a power supply and the differential output terminals. The output circuit further includes a third differential pair of transistors driven by a third current source and differentially receiving second control signals and a fourth differential pair of transistors driven by a fourth current source and differentially receiving third control signals. An output pair of the third differential pair of transistors is connected between one of the differential output terminals and the power supply.

Abstract: A method and current drive circuit is provided that accepts a positive voltage input signal and supplies power to a load from a negative voltage rail.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: Integrated circuits for an output driver and an output interface, as well as a method for operating an output driver, are described. In an embodiment of an integrated circuit for an output driver, a differential driver is coupled to a first single-ended driver at a first output node of the first single-ended driver and the differential driver. A second single-ended driver is coupled to the differential driver at a second output node of the second single-ended driver and the differential driver. The first single-ended driver provides a first source termination resistance for an open-drain mode of the differential driver, and the second single-ended driver provides a second source termination resistance for the open-drain mode of the differential driver.

Abstract: A method of operating inverter may include providing a load transistor and a driving transistor connected to the load transistor wherein at least one of the load transistor and the driving transistor has a double gate structure, and varying a threshold voltage of the at least one of the load transistor and the driving transistor having the double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter.

Abstract: Embodiments of an integrated circuit driver, a method for operating integrated circuit driver, and predrivers are described. In one embodiment of the integrated circuit driver, a bias control circuit provides a bias signal for a first mode and a second mode. The bias signal has a first voltage level associated with operation in the first mode and a second voltage level associated with operation in the second mode. An output driver circuit receives the bias signal. In the first mode, the output driver circuit operates as a supply referenced driver, and in the second mode, the output driver circuit operates as a ground referenced driver.

Abstract: An electronic apparatus is provided. A PCB has first and second signal paths therein. First and second fingers are disposed on the first and second signal paths, respectively. A controller is coupled to a first memory via the first finger and a second memory via the second finger, and accesses the first and second memories through the first and second signal paths, respectively. The first and second signal paths share a common segment between the controller and a branch point. First and second components are disposed between the first finger and the branch point and between the second finger and the branch point, respectively. The distances between the first component and the branch point and between the second component and the branch point are smaller than or equal to the distance between the first component and the first finger and between the second component and the second finger, respectively.

Abstract: Disclosed is a switch driving circuit for controlling the switching operation of a switch. The switch driving circuit includes a driver generating a normal gate signal for controlling the switching operation of the switch, and a gate signal correction circuit comparing the normal gate signal with a gate signal applied to a gate electrode of the switch so as to correct the gate signal in accordance with the comparison.

Abstract: A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive circuits is selected as the selected bus drive circuit. When a logical value corresponding to the data input to be output is the same as a logical value that has been held by the bus holder and output to the common bus, the selected bus drive circuit stops outputting the logical value corresponding to the data input to the common bus. With this configuration, it is possible to eliminate the unnecessary output of the selected bus drive circuit, and to reduce unnecessary current consumption compared to the conventional semiconductor integrated circuit.

Abstract: An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.

Abstract: A semiconductor device includes a core circuit including an integrated circuit; output drivers, each including sub-drivers to output digital data transferred from the core circuit, as output data; and a selector that selects a sub-driver to be driven from among the plurality of sub-drivers. Each of the sub-drivers includes: an output transistor connected between a first power supply and an output wiring line to allow the output data to rise or fall according to the digital data; and a switching transistor and a slew-rate control transistor which are connected in series between a gate of the output transistor and a second power supply. The switching transistor turns on or off the output transistor according to the digital data. A gate potential adjusted to determine a slew rate for rise or fall of the output data is selectively provided by the selector to each slew-rate control transistor.

Abstract: An output switch driving capability booster which may effectively reduce a propagation delay in an output switch with an independently controllable output transition change rate. A delay controller coupled to the output switch may be used to control the propagation delay. The delay controller may have a switch which may be switched on and off approximately simultaneously with the output switch, and a resistance device which may be adjusted to reduce the propagation delay.

Abstract: Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.

Abstract: In one embodiment, a circuit for providing a tail current for a line driver includes an adjustable current source. The adjustable current source includes a number of current source cells coupled together in a parallel configuration, where the current source cells are configured to provide the tail current for the line driver in response to a digital control signal. The circuit can further include a digital core coupled to the adjustable current source, where the digital core provides the digital control signal. The digital control signal provides a number of bits, where each bit controls one of the current source cells. In one embodiment, a current source cell can comprise a number of current source sub-cells. The current source cells can be configured to provide the tail current for the line driver in response to the digital control signal when the line driver is operating in a class AB mode.

Abstract: An integrated circuit (IC) includes an input/output (I/O) circuit supporting high-speed operation and multiple I/O logic-level swings. The I/O circuit includes a first output signal chain to generate outputs with a first logic level swing, and a second output signal chain to generate outputs with a second logic level swing. The outputs of the first output signal chain and the second output signal chain are connected to a same output pad of the IC. Transistors in the first output signal chain and the second output signal chain are fabricated using corresponding gate oxide characteristics. The second output signal chain includes protection circuitry to prevent transistors in the second output signal chain from being subjected to voltage stresses beyond a safe limit. An input circuit in the I/O circuit similarly includes multiple input signal chains to enable reception of input signals of different logic-level swings from a same input pad.

Abstract: A programmable input/output circuit includes a programmable output circuit configured to drive an output signal to an input/output pad at a plurality of voltages. The programmable input/output circuit further includes a programmable input configured to detect an input signal from the input/output pad at a plurality of voltages. The voltage levels of the input and output circuits may be independently and dynamically controllable.

Abstract: A transceiver circuit supports a bidirectional mode and the bidirectional transceiver circuit is signal-compatible with JEDEC SSTL 2. A differential transceiver circuit supports a bidirectional mode and is also signal-compatible with JEDEC SSTL 2. Finally, transceiver circuits which, in interaction with the bidirectional transceiver circuits, allow a bus system to be set up.

Abstract: In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver. If the receiver circuit is receiving a differential input, one of the current sources may be used. If the receiver circuit is receiving a single-ended input, both of the current sources may be used. A larger gain may thus be provided for the single-ended input as compared to the differential input.

Abstract: A semiconductor output circuit, an external output signal generation method and a semiconductor device that suppress variation in an external output signal caused by a decrease in power supply voltage. An output section changes electric potential of an external output signal EB according to a change in electric potential of an internal input signal A from ground to VDD or from VDD to the ground. A differential section outputs an output signal corresponding to the external output signal EB and a predetermined reference signal VREF. The differential section functions as a voltage follower so that the electric potential of the external output signal EB will correspond to the predetermined reference signal VREF. As a result, variation in output voltage VOL at a low voltage side of the external output signal EB is suppressed.

Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage in the buffer circuit and is operative to generate a first control signal indicating a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage over variations in PVT conditions to which the buffer circuit may be subjected. The compensation circuit further includes a control circuit generating first and second sets of digital control bits for compensating the pull-up and pull-down portions in the output stage over prescribed variations in PVT conditions. The second set of digital control bits is generated based at least on the first set of digital control bits and the first control signal.

Abstract: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

Abstract: A complementary high voltage switched current source circuit has a complementary current source pair, wherein a first of the current source pair is coupled to a positive voltage rail and a second of the current source pair is coupled to a negative voltage rail. A digital logic-level control interface circuit is coupled to the complementary current source pair and to the positive voltage rail and the negative voltage rail. A pair of high voltage switches is coupled to the complementary current source pair and the digital logic-level control interface circuit and controlled by the digital control interface circuit.

Abstract: A method controls a power MOS transistor having a control terminal and a load path, the load path connected in series with a load between voltage supply terminals, wherein a power supply voltage between the voltage supply terminals imposes a load voltage across the load and a load path voltage across the load path of the power MOS transistor. The method includes generating a control current for the control terminal during a switching process when the power MOS transistor changes switching states. The control current is dependent on the power supply voltage and on at least one of the group consisting of the load path voltage and the load voltage.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.

Abstract: An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor.

Abstract: A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

Abstract: According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.

Abstract: A system and a method for communicating data at a rate exceeding about a gigabit per second is described. The system may include circuitry and a current-sourcing module. The circuitry may include an output couplable to a load. The circuitry may output from the output a low voltage differential signal having a first current that drives the load from a first voltage at a first time to a second voltage at a second time. The current-sourcing module may apply a second current to the output at a third time, which occurs at about the first time.

Abstract: An inverter includes an input inverter having a high-resistance load and a first transistor and an output buffer including second and third transistors coupled in series. A power supply voltage is provided to satisfy an inequality VDD1>VDD2+Vth where VDD1 is the power supply voltage of the input inverter, VDD2 is the power supply voltage of the output buffer, and Vth is the threshold voltage of the transistors. Use of the high-resistance load allows an output waveform to rise and fall quickly, as well as reduces current consumption.

Abstract: An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side.

Abstract: A microprocessor control unit (MCU) is mounted on a printed circuit board. The MCU includes first and second clocked serial interface (CSI) circuits. The first CSI circuit is configured to serially transmit a first xCP packet to a first encoder circuit, which in turn is configured to generate an encoded first xCP packet as a function of the first xCP packet and a first clock signal. A first low voltage differential signal (LVDS) circuit is coupled to the first encoder circuit and configured to serially receive the encoded first xCP packet therefrom. The first LVDS circuit is configured to generate a first differential signal as a function of the encoded first xCP packet.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.

Abstract: An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line.

Abstract: An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.

Abstract: The present invention discloses a capacitive high-side switch driver for a power converter. The capacitive high-side switch driver according to the present invention includes an inverter and two alternately conducting totem-pole buffers with complementary duty cycles. The duty cycles alternate in response to an input signal. The capacitive high-side switch driver further includes a low-side transistor and a high-side transistor. Once the low-side transistor is turned on, a bootstrap capacitor is charged to create a floating voltage via a charge-pump diode to supply power for the high-side switch driver. To supply additional power for the high-side switch driver, differential signals are produced to further charge the bootstrap capacitor via a bridge rectifier. The capacitive high-side switch driver utilizes a programmable load to provide variable impedance. Furthermore, an under-voltage protector supervises the supply voltage to ensure a reliable gate driving voltage.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.