Abstract: In accordance with an embodiment, a circuit includes a first and a second switching transistors configured to be coupled in series between a first reference voltage terminal and a transformer. The circuit also includes a first diode coupled between a first drain of the first switching transistor and a first input terminal. The first diode is configured to clamp a voltage of the first drain to a voltage of the first input terminal. The circuit further includes a switching circuit coupled between the second switching transistor and the first input terminal. The switching circuit is configured to connect a second source of the second switching transistor to a second gate of the second switching transistor when a voltage of the second source exceeds the voltage of the first input terminal.

Abstract: A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.

Abstract: A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse.

Abstract: Various methods and devices that involve electronic circuits are disclosed. A disclosed method includes buffering an input signal using a first buffer. The first buffer is powered by a supply voltage and a reference voltage. The method also includes buffering the input signal using a second buffer. The second buffer is powered by the reference voltage and a ground voltage. The method also includes level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter, and level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter. The voltage range is larger than a delta between the supply voltage and the reference voltage. The reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage.

Abstract: A drive circuit includes a first output node for connection to the control electrode of the semiconductor switch, a voltage supply circuit, and a first switching stage connected to the voltage supply and a second switching stage connected to the voltage supply. A first resistor network is connected between the first switching stage and the first output node. A second resistor network is connected between the second switching stage and the first output node. A control logic is designed to generate control signals for the guiding of the first switching stage and the second switching stage in such a way that in a first operating mode of the semiconductor switch the semiconductor switch is driven only via the first resistor network, and in a second operating mode of the semiconductor switch the semiconductor switch is driven only via the second resistor network or both resistor networks.

Abstract: Disclosed are a VCOM generation circuit and a liquid crystal display. The VCOM generation circuit has a voltage divider circuit coupled between a power source input end of the VCOM generation circuit and a ground, and a voltage output end; an operational amplifier output circuit, and one input end is coupled to the voltage output end of the voltage divider circuit, and an output end is a VCOM input end of a liquid crystal display, employed for outputting a liquid crystal drive reference voltage VCOM as the liquid crystal display functions to charge a liquid crystal layer; a delay circuit, coupled between the one input end of the operational amplifier output circuit and the ground, and employed for delaying a change rate of the VCOM as the operational amplifier output circuit outputs the VCOM.

Abstract: A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.

Abstract: In the present invention, scope search can be effectively performed in a database having encrypted registration information. A plurality of values, first identification information to identify the plurality of values, and a key are accepted as input. A value group is generated from the plurality of values. The value group is treated as a word group, and a secure index is generated from the word group, the first identification information, and the key. On the basis of a value to be retrieved and a key, trapdoor information for the value to be retrieved is generated. With respect to the generated secure index, a secure index assessment process is performed using the trapdoor information. When the value to be retrieved is assessed to be contained in the secure index as a result of the assessment process, second identification information to identify the secure index is output.

Abstract: A transmitter operates by receiving a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and includes a driving circuit that generates an output signal according to a driving control signal, a swing adjustment block that adjusts a swing width of the output signal to be lower than a difference between the first power supply voltage and the second power supply voltage in response to a swing control signal, and a swing control signal generation circuit that generates the swing control signal based on the output signal.

Abstract: Provided herein are apparatus and methods for enhancing bandwidth in trench isolated integrated circuits. In certain configurations, an auxiliary trench forming floating regions between moat isolation regions can isolate parasitic sidewall capacitances of active device regions from ground or AC ground. In this manner the active device regions are merged by the auxiliary trench so as to improve circuit bandwidth and enhance circuit performance. When arranged or combined within a circuit branch, transistors within each floating moat can operate with relatively small parasitic displacement current and can have improved performance.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: In accordance with an embodiment, a method in a voltage converter includes, in each of successive drive cycles, switching on for an on-period a first electronic switch connected in series with a primary winding of a transformer. Before first electronic switch is switched on, the transformer is pre-magnetized for a pre-magnetizing period, where there is a first delay time between an end of the pre-magnetizing period and a beginning of the on-period.

Abstract: A drive circuit includes a signal source that outputs an AC signal, a voltage generator circuit that includes a differential amplifier that generates a first AC voltage with a constant amplitude from the AC signal and outputs the first AC voltage to one end of an external load, and a voltage-to-current converter circuit that is connected to another end of the external load and supplies an AC current with a constant amplitude in opposite phase to the first AC voltage to the external load in accordance with the AC signal.

Abstract: According to one embodiment, there is provided a switching element driving power supply circuit that converts a main circuit voltage into a driving voltage of power-converting switching elements. The circuit includes a plurality of insulating power supplies, and a plurality of switching element driving power supply units. The insulating power supplies have respective direct-current input circuit ends connected in series, respective input-side circuits and output-side circuits insulated from each other, and respective output circuit ends connected in parallel. The power supply units are connected in parallel with the output circuit ends, and supplying power to the gate driving circuits of the power conversion switching elements.

Abstract: A tracking current sensing system is described. The system may include a first electrical sensing element configured to receive a first electrical signal and a second electrical signal from a high side switch of a half-bridge circuit and output an electrical signal based on the received electrical signals. The system may also include a second electrical sensing element configured to receive a first electrical signal and a second electrical signal from a low side switch of the half-bridge circuit and output an electrical signal based on the received electrical signals. The system may further include a current evaluation circuit that is configured to receive the electrical signal output by the first electrical sensing element and the second electrical sensing element, and output a bias output current that is continuous when the half-bridge switches between the high side switch and the low side switch.

Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance.

Abstract: A drive device includes: an on-side circuit turning on a power switching element; an off-side circuit turning off the power switching element; and a protection circuit controlling a gate current of the power switching element. The protection circuit includes: a constant-current circuit that defines a constant current for drawing a gate charge of the power switching element; a protection switch that controls electrical connection between the constant-current circuit and the gate of the power switching element; and a collector current detector. The collector current detector turns off the on-side circuit to disconnect the power switching element from the main power supply, and turns on the protection switch after a predetermined time has elapsed from when the current value of the collector current of the power switching element exceeds a first threshold.

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

Abstract: Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).

Abstract: A circuit for conveying information from a sender component to a receiver component is provided. The sender component is a high side component and the receiver component is a low side component or the sender component is a low side component and the receiver component is a high side component. The low side component is arranged to drive a first electronic switch of a half bridge and the high side component is arranged to drive a second electronic switch of the half bridge. The circuit includes a first voltage-decoupling device and a second voltage-decoupling device that are arranged such that a voltage conveyed from the sender component to the receiver component is modulated by the sender component and conveyed across the first voltage-decoupling device and the second voltage-decoupling device depending on the information.

Abstract: A semiconductor device includes a first nonlinear element, an differential amplifier that generates a differential signal from a signal output by the first nonlinear element; a first and second insulating elements that are connected to a non-inverting signal output terminal and an inverting signal output terminal of the differential amplifier, respectively; first to third nonlinear elements each outputting a first logic level if the received signal is equal to or larger than a given threshold value, and outputting a second logic level if the received signal is smaller than the given threshold value; and a logic circuit that outputs the logic level output by the second nonlinear element if the logic levels output by the second and third nonlinear elements are different from each other, and makes the logic level of the output signal unchangeable when the second and third nonlinear elements output the same logic level.

Abstract: A method and system of driving an LED load. There is a power stage that is configured to deliver a level of current indicated by a control signal to the LED load when a PWM signal is ON and stop delivering the level of current when the PWM signal is OFF. There is a feedback circuit that is configured to generate the operating point signal, which causes the power stage to deliver a level of current indicated by the control signal, when the PWM signal is ON. A store and hold circuit is configured to store an information indicative of a level of the operating point signal just after the PWM signal is turned OFF and cause the operating point signal to be at that level just before the PWM signal is turned ON.

Abstract: A current mirror circuit includes a first transistor connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor, a current source connected to the drain and the gate of the first transistor, the current source being configured to generate a predetermined first output current, a sample and hold circuit having an input connected to the gate of the first transistor, a second transistor connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit, and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency to attenuate bias noise from the first transistor in a second output current from the second transistor.

Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.

Abstract: During operation, a supply voltage and the reference voltage power a novel multi-level pulse generator circuit. The multi-level pulse generator circuit generates voltage pulses of varying magnitude from a respective output port. For example, the multi-level pulse generator circuit produces respective pulses to have magnitudes that fall inside and outside of a range defined by the supply voltage and the reference voltage. Expansion of the pulse magnitudes to be outside of the range as defined by the supply voltage and the reference voltage increases noise immunity and therefore enables a respective transmitter to transmit data at higher bandwidth. The multi-level pulse generator circuit can be fabricated using a set of multiple transistors of only a single type in which each of the multiple transistors in the set has a corresponding oxide breakdown voltage that is substantially less than the respective magnitude that falls outside of the range.

Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.

Abstract: In a gate driver for driving a first transistor with a constant current, a constant current circuit supplies the constant current to a gate of the first transistor. A second transistor has a gate supplied with a gate reference voltage as a reference for a drive voltage to turn ON the first transistor and is connected in a forward direction in a path from the constant current circuit to the gate of the first transistor. A controller drives the first transistor by operating the constant current circuit when an ON instruction is inputted. The controller sets the gate reference voltage to a first value when the ON instruction is inputted and then changes the gate reference voltage to a second value greater than the first value when a predetermined timing comes under a condition where the first transistor is not in an overcurrent state.

Abstract: The embodiments described herein relate to an improved circuit technique for a multiple input regulator circuit having multiple power paths therein. The multiple input regulator circuit may be configured to minimize integrated circuit area by utilizing a single power transistor in the power path from each of the power sources to the output of the regulator circuit. The single power transistor is adapted to provide both power source selection and power source regulation functions, thus replacing the power selection transistor and the power regulation transistor of conventional designs.

Abstract: A latch circuit, a receiver circuit, a semiconductor apparatus, or a system may be provided. The latch circuit may include a delay configured to delay an input signal and generate a delay signal. The latch circuit may include a control signal generator configured to enable a control signal based on the input signal and the delay signal, and disable the control signal based on a reset signal. The latch circuit may include a gating circuit configured to output, based on the control signal, the input signal and the delay signal to an output node. The latch circuit may include a latch configured to latch, based on a strobe pulse, an output of the gating circuit and generate an output signal.

Abstract: An electronic circuit has a current generator circuit that generates a two-state output current signal for which a transition between states is altered.

Abstract: A driver for performing efficient low-power high-swing modulation, which comprises a first plurality of N controllable switching elements and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each divider consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of

Abstract: In a DC-DC converter that can be operated in an asynchronous manner with a rectification diode connected to an external terminal, a conducting path through a transistor that is turned on and off according to a clock signal is provided between a bootstrap circuit, which is composed of a bootstrap diode and a bootstrap capacitor, and a ground terminal.

Abstract: A slope control circuit is connected between a replica circuit and a controller area network bus. The replica circuit generates an upper and a lower feedback signal. The slope control circuit receives and is driven by the feedback signals for controlling a voltage slope of a high-level output and a low-level output. The slope control circuit comprises an upper and a lower driving circuit, individually connected between the replica circuit, the high-level output and the low-level output. The upper driving circuit and the lower driving circuit respectively include at least one charging and discharging circuit. By controlling the charging and discharging circuit, the present invention controls decreasing voltage slope of the high-level output to be symmetric to increasing voltage slope of the low-level output, and delay time of the circuit switching between different operating modes to be equivalent.

Abstract: A turn-off overvoltage limiting for IGBT is described herein. The injection of a sample of the overvoltage across the IGBT in the gate drive to slow down the slope of the gate voltage decrease only during the overvoltage above a predetermined value is described herein. Techniques to increase the parasitic inductance to allow the control to limit an overvoltage at turn off of the second IGBT are also described herein.

Abstract: Systems and methods relating to voltage monitoring across isolation barriers are disclosed herein. In one example embodiment, an isolation system includes a low voltage circuit portion including a first control logic portion, and a high voltage circuit portion including a second control logic portion and an analog-to-digital converter portion. The system further includes a first transistor device having a first terminal coupled at least indirectly to a first connection having a first voltage level and a second terminal coupled at least indirectly to a second connection having a second voltage level. The first control logic portion governs provision of an output signal generated based at least indirectly upon the second voltage level. Due to a galvanic barrier, the output signal can be provided for receipt by another device in a manner that avoids exposure of that device to an undesirably high current or power level.

Abstract: A method for controlling a configuration in an integrated circuit device with at least one controllable input/output port having a data output driver, a data input driver, a controllable pull-up resistor, a controllable pull-down resistor, each connected with an external pin of the integrated circuit device, has the steps of: enabling only the pull-up resistor and reading the associated input through the data input driver as a first bit; enabling only the pull-down resistor and reading the associated input through the data input driver as a second bit; tri-stating the first port and reading the associated input through the data input driver as another bit; encoding a value from the read bits; and determining a firmware operation form the encoded value.

Abstract: A driver device is for switching on and off a transistor for supplying a load by driving a control electrode of the transistor. The driver device includes a first terminal connected to the control electrode of the transistor, a second terminal connected between the transistor and the load, and a current-discharge path coupled to the first terminal. The current-discharge path includes a diode and is activated when the transistor is switched off. The diode becomes non-conductive to interrupt the current-discharge path when the voltage on the second terminal reaches a threshold value.

Abstract: Systems, media, methods, and platforms providing video processing for generating and sharing lip-sync videos comprising: presenting an interface allowing a user to select audio content; presenting an interface allowing a user to capture video content; presenting an interface allowing a user to synchronize the audio content with the video content; synthesizing the video content and the audio content to generate a new lip-sync video; automatically sharing the lip-sync video to a social media platform; and providing a lip-sync video feed within a social network.

Abstract: Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.

Abstract: The invention concerns a high voltage driver comprising: first and second cascoded transistors (102, 104) adapted to generate an output signal (VOUT) based on a first voltage signal (VSL) having a first voltage range and on a second voltage signal (VSH) having a voltage range shifted with respect to the first voltage range, the output signal having a second voltage range greater than the first voltage range; and a pulse generator (128) comprising a passive high-pass filter adapted to generate voltage pulses based on at least one of the first and second voltage signals and to provide the voltage pulses to a control node of at least one of the first and second transistors.

Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

Abstract: A variable gain amplifier circuit includes a differential pair of transistors and a variable current source circuit. The differential pair of transistors generates an output signal based on an input signal. The variable current source circuit is coupled to the differential pair of transistors. A gain of the output signal relative to the input signal varies in response to variations in a bias current through the variable current source circuit. The variable gain amplifier circuit maintains a common mode voltage of the output signal substantially constant in response to the variations in the bias current through the variable current source circuit.

Abstract: An output MOS transistor has a drain connected with a power supply and a source connected with an output terminal. The short-circuit MOS transistor has a source connected with the output terminal. The short-circuit MOS transistor is formed in a semiconductor substrate connected with the power supply. A switching device is formed in a semiconductor region which is formed in the semiconductor substrate, and contains a first diffusion layer connected with the gate of the output MOS transistor and a second diffusion layer formed in the semiconductor region and connected with the drain of the short-circuit MOS transistor.

Abstract: A method for actuating a controllable semiconductor switch by switching the switch on an off in phases in a controlled manner using a control signal is disclosed. The method includes starting a time measurement at the beginning of at least one phase of the phase-wise on-and-off switching procedure to ascertain a time duration, wherein the time measurement is continued until a phase following the at least one phase of the phase-wise on-and-off switching procedure begins. The ascertained time duration is compared with a specified maximal time duration. If the ascertained time duration exceeds the specified maximal time duration, the semiconductor switch is actuated such that the semiconductor switch is switched into a specified operating state.

Abstract: In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal.

Abstract: Provided is a DC-DC converter with improved power conversion efficiency. A transistor which is incorporated in the DC-DC converter and functions as a switching element for controlling output power includes, in its channel formation region, a semiconductor material having a wide band gap and significantly small off current compared with silicon. The transistor further comprises a back gate electrode, in addition to a general gate electrode, and a back gate control circuit for controlling a potential applied to the back gate electrode in accordance with the output power from the DC-DC converter. The control of the potential applied to the back gate electrode by the back gate control circuit enables the threshold voltage to decrease the on-state resistance when the output power is high and to increase the off-state current when the output power is low.

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract: A circuit includes a first power node that carries a first supply voltage having a first voltage level and a second power node that carries a second supply voltage having a second voltage level less than the first voltage level. A voltage driver has a first plurality of transistors, an input node for an input signal, and an output node, and a current driver has a second plurality of transistors. The current driver injects or extracts an adjustment current into or out of the output node. The first plurality of transistors and the second plurality of transistors electrically couple the output node and the current driver to the first power node in response to the input signal being at a first logic state, and electrically decouple the output node and the current driver from the first power node in response to the input signal being at a second logic state.

Abstract: The invention provides a scan driving circuit for an oxide semiconductor thin film transistor. The scan driving circuit for an oxide semiconductor thin film transistor includes multiple cascade connected GOA units and a shared auxiliary inverter. Each of the GOA units includes a main inverter. The auxiliary inverter is electrically connected to each main inverter to form corresponding pull-down holding parts for the respective GOA units, which can achieve the sharing of the pull-down holding parts of the multiple stages GOA units, the number of TFT elements can be reduced and therefore GOA layout space as well as circuit power consumption can be reduced.

Abstract: A voltage mode transmitter is provided. The voltage mode transmitter includes a control unit and a resistor ladder circuit. The control unit receives a first signal and delays an inverse of the first signal for a time period to obtain a second signal. The resistor ladder circuit is configured to sum up products of the first signal or the second signal and a plurality of weights, thereby generating an output signal. The resistor ladder circuit includes an input terminal, multiple first resistors and a second resistor. The output terminal is configured to output the output signal. Each of the first resistors is coupled between the output terminal and the control unit and receives the first signal or the second signal. The resistances of the first resistors are 2R, 4R . . . and 2nR respectively, where R is a reference resistance. The resistance of the second resistor is 2nR.