Abstract: An integrated semiconductor image-rejection mixer having high linearity and high gain. In addition to the components of a classic image-rejection architecture, the present mixer has a high-frequency current-diverting stage that permits the operation of the output stage with high conversion gain and sufficient headroom for good linearity, even in cases where the supply voltage is relatively low (such as 3 V). The conversion gain of the mixer and its image-rejection performance can be changed by changing the load resistances and the elements of the output polyphase network, with minor effects on linearity and no change in power consumption or DC levels. The power consumption of the image-rejection mixer is low because no additional DC current is required for buffers or amplifier stages.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: Disclosed is a heterodyne receiver for low noise and image frequency repression, comprising: a low noise amplifier for receiving an input signal from an antenna and amplifying the signal while reducing a noise figure of the input signal; and a frequency converter for receiving both the input signal outputted from the low noise amplifier and a local oscillation signal, filtering the signals to repress gain of the input signal at an image frequency band and increase gain of the input signal at a signal frequency band, and converting the frequency of the signals to the intermediate frequency band.

Abstract: A player apparatus for playing an input signal after band-extending the input signal includes: an extension controller to determine an extension start band for the input signal in accordance with information relating to the input signal; and a band divider to divide the input signal into a plurality of sub-band signals. The frequency band is extended on the basis of a plurality of the sub-band signals on a side lower than the extension start band, among the plurality of sub-band signals into which the input signal is band-divided by the band divider.

Abstract: In one embodiment, a local oscillator and mixer architecture may include a frequency divider having I and Q channel master storage elements formed of devices of a first size, and I and Q channel slave storage elements formed of devices of a second size, where the second size is smaller than the first size. In such manner, power consumption may be reduced while reducing phase noise in signals provided from the frequency divider to the corresponding mixer.

Abstract: The invention relates to an automation device, in which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted. A sequential sequence of equidistant samples of a sinusoidal time profile is stored in the memory unit (150), such that it can be called up, in such a manner that the samples can be output using either the clock of the first clock generator or the clock of the second clock generator, depending on the data bit-stream.

Abstract: Accurate correction of a local clock that avoids excessive drift in the local clock while avoiding an accumulation of quantization errors. A local clock according to the present techniques generates a local time by accumulating a sequence of rate coefficients selected from a plurality of rate coefficients using a series of progressively longer replacement periods.

Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.

Abstract: A frequency-controllable oscillator, having an oscillation device in which the oscillation frequency is controlled on the basis of a feedback current or voltage; a constant current source circuit; a charge device which charges a capacitor with a constant current from the constant current source circuit on the basis of an oscillation output from the oscillation device; and a control device which generates the current or voltage for control of the oscillation frequency of the oscillation device on the basis of electric charge stored in the capacitor and a predetermined reference value and which includes an integrator formed of an operational amplifier and an integrating capacitor, the Integrator performs integration on the basis of the charged voltage across the capacitor and the predetermined reference value, and the current or voltage for control of the oscillation frequency of the oscillation device is generated on the basis of an integrated output from the integrator.

Abstract: A frequency generator apparatus and a control circuit thereof are provided. The frequency generator apparatus comprises the control circuit and a frequency generator, wherein the control circuit contains an electric fuse (efuse). The control circuit outputs an enabling signal according to the state of the efuse. The frequency generator is coupled to the control circuit, receives the enabling signal, and decides to output a frequency signal or not according to the enabling signal.

Abstract: A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).

Abstract: An apparatus for improving dynamic range includes a frequency down-conversion module that receives an input signal and a bias circuit. The bias circuit includes a first resistor and a second resistor. The first resister has a first terminal coupled to a bias point and a second terminal coupled to a first voltage reference. The second resistor has a first terminal coupled to the bias point and a second terminal coupled to a second voltage reference. The bias point is coupled to the input signal. The frequency down-conversion module outputs a down-converted output signal. The bias circuit thereby adjusts a voltage of the input signal.

Abstract: The invention relates to a mixer circuit comprising an input node for receiving an input signal, a first output node 202, and a second output node 203, voltage to current conversion means and switching means operatively coupled to each other and to the input node, the first output node and the second output node to generate a mixed input signal at the first output node and the second output node in response to an oscillator signal. In an embodiment the voltage to current conversion means comprises a first and a second voltage to current converter, implemented as N-MOSFETs M2 and M3, with their gates connected to the input node. The drain of M2 is connected to the first output node 202, while the drain of the M3 is connected to the second output node M3. The source of M2 is connected to the switching node 221, while the source of M3 is connected to the second switching node 222.

Abstract: The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the high-frequency clock signal, and wherein an output terminal (6) for outputting a frequency-divided clock signal is connected to the output of one cell of the loop of series-connected cells.

Abstract: A mixed type frequency compensating circuit is disclosed. The mixed type frequency compensating circuit includes an integral component sub-circuit of a voltage-amplifier-type frequency compensating circuit and a proportional component sub-circuit of a transconductance-amplifier-type frequency compensating circuit. The integral component sub-circuit amplifies an input voltage signal in a voltage mode. The proportional component sub-circuit amplifies the input voltage signal in a current mode. Accordingly, the mixed type frequency compensating circuit may occupy a small area in a semiconductor integrated circuit.

Abstract: A demodulation apparatus that can support various oscillation frequencies. The portable phone device includes a frequency synthesizer for generating a local-oscillation signal having a local oscillation frequency for converting the frequency of an input receiving signal into an intermediate frequency based on an oscillation signal generated by an TCXO and a synchronization hold portion provided with an NCO for generating a signal having a predetermined frequency based on the oscillation signal generated by TCXO. The frequency synthesizer makes the local oscillation frequency variable by setting the dividing ratio variable in accordance with an arbitrary oscillation frequency so that the intermediate frequency remains within a predetermined range regardless of the oscillation frequency, and an NCO makes the frequency of the signal variable by setting the dividing ratio variable in accordance with the oscillation frequency.

Abstract: A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

Abstract: Frequency translation and applications of same are described herein, including cable modem applications. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same. Furthermore, QAM, QPSK, and other modulation techniques are also described.

Abstract: A controller and method changing a frequency of a control (or carrier) signal in accordance with a waveform that periodically changes within a first frequency range from a frequency fc1 to a frequency fc2, where the frequency fc1 is smaller than the frequency fc2, and a second frequency range from a frequency fc3 to a frequency fc4, where the frequency fc3 is smaller than the frequency fc4. The frequencies fc1 and fc4 satisfy the inequalities (n?1)·fc4?n·fc2 and n·fc3?(n+1)·fc1 and/or satisfy an approximate expression n·fc4?(n+1)·fc1 where n is an integer. The frequencies fc2 and fc3 satisfy the inequalities n·fc2?fs??fs and fs+?fs?n·fc3 where fs±?fs represents a predetermined frequency band.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: An apparatus and method are provided that enable a computing device to make graceful power state transitions that do no impose unnecessary power surge compensations requirements on associated power sources. The apparatus has power control logic that is configured to determine if the computing device is to enter a low power state. The power control logic includes a plurality of stop signals. Each of the plurality of stop signals sequentially indicates that a corresponding clock signal be stopped, where the corresponding clock signal is operatively coupled to a corresponding sector logic element within the computing device.

Abstract: A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock signal; and an enable signal generator electrically connected to the frequency divider for dividing the frequency-divided signal to produce at least one enable signal. The frequency divider switches the frequency of the system clock signal at a time period corresponding to a pulse edge of the frequency-divided signal.

Abstract: A mixer circuit (50) includes a first switching mixer (20A) with a first desired signal input (RF+ and RF?), a first switching signal input (LO+& LO?), and a first output (IF+ and IF?), a second switching mixer (20B), and a third switching mixer (20C) with corresponding desired signal inputs, switching signal inputs, and outputs. An overall input signal to the mixer circuit is fed to an input port (56) of the first switching mixer, an output from an output port (57) of the first switching mixer is fed to an input port (58) of the second switching mixer, the output from an output port (59) of the second switching mixer is fed to an input port (60) of the third switching mixer, and an overall output of the mixer circuit can be an output from an output port (62) of the third switching mixer.

Abstract: A circuit and corresponding method for doubling the frequency of an input signal, even when the input signal is of low frequency or a square wave. The input signal is applied to a phase-shifting circuit that produces a pair of output signals that are theoretically 90° apart in phase, but may lack the desired form if the original input signal is of low frequency. The waveforms of the two output signals are enhanced in latching hysteresis buffers that produce more uniformly squared waves, with zero crossings corrected to be more exactly 90° apart and with desirably steep state transitions. The enhanced-waveform output signals are coupled to an exclusive OR (XOR) gate to produce a double-frequency output.

Abstract: In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Abstract: A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a refresh interval. The refresh interval depends on a frequency of an oscillating signal. A refresh timer adjusts the frequency of the oscillating signal based on changes in the temperature to adjust the refresh interval.

Abstract: A digital control device for tracking a sine wave according to the present invention has a compensator, a control object and a feedback gain. An input into the compensator is a signal obtained by subtracting a control quantity from a reference value. An input into the control object is a signal obtained by subtracting an output of the feedback gain from an output of the compensator. A transfer function of the compensator is (k2z+k1)/(z2?2z cos ?T+1), where ? is an angular frequency, T is a sampling period, z is a z operator, and k1 and k2 are constants. Thus, a second-order compensator can be configured, with which a sinusoidal reference waveform can be tracked simply and with high accuracy.

Abstract: Delta/sigma frequency discriminator (1) for converting a frequency (Fv) of an input signal into a digital output signal (C) comprising a frequency divider (8) which divides the input signal at a frequency dividing ratio which can be switched in dependence on the digital output signal (C), with at least one sampling register (12) which samples the divided input signal by means of a reference clock signal for generating the digital output signal (C), and with a dither circuit (15) which varies the clock period (T) of the reference clock signal so that interfering modulation tones in the signal spectrum of the digital output signal (C) are suppressed.

Abstract: A start signal output circuit having an RF/DC conversion circuit to which radio frequency power (RF) of specified frequency is inputted and from which a direct current potential (DC) is outputted, comprises a detection/amplification circuit 210 which includes a voltage doubler wave-detector circuit 10 configured including a sensing diode Q1 (Tr34) for sensing the RF power, a differential amplifier including differential pair transistors Tr31 and Tr32, and a current mirror circuit. A base current of one Tr31 of the differential pair transistors is brought into substantial agreement with a DC component of a current flowing through the sensing diode Q1 (Tr34). A total of currents flowing through the differential pair transistors Tr31 and Tr32 is regulated to a substantially constant value by the current mirror circuit. Thus, the start signal output circuit which is small in size, high in sensitivity and low in power consumption can be realized.

Abstract: Channelizing an applied current and applying a voltage to the channelized current enables switching of the applied current. According to the present invention, an applied current enters through a signal input carrier (12) and is channelized by a plurality of lateral potential wells created by a plurality of polysilicon fingers gates (14). A first voltage is applied to a first set of the plurality of polysilicon finger gates (32) and a second differential voltage is applied to a second set of the plurality of polysilicon finger gates (34), which results in a differential current flow among the lateral potential wells beneath the first and second sets of polysilicon fingers (32, 34), respectively. The differential current then flows to first and second signal output carriers (40, 42).

Abstract: A clock frequency multiplier is provided. The clock frequency multiplier comprises a tracking circuit, a pulsing circuit, and a shaping circuit. The tracking circuit receives a clearing signal and a reference clock signal, outputs the quotient of the number of cycles of the reference clock signal in a cycle of the clearing signal divided by a first predetermined value. The pulsing circuit outputs a pulsing signal wherein the frequency of the pulsing signal is the frequency of the clearing signal multiplied by the first predetermined value. The shaping circuit divides the frequency of the pulsing signal by a second predetermined value and shapes the pulsing signal into a clock signal with a predetermined duty cycle, and outputs the divided and shaped pulsing signal as an output clock signal.

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency (IF) signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: The invention relates to a mixing circuit for mixing a first signal RF with a second signal LO including a conversion stage T3 to convert the first signal RF into a current, a mixing core T1 and T2 to mix said current with the second signal LO, said mixing core being loaded via at least one load element ZC. Said circuit includes noise optimization means taking into account the contribution of the load element or elements ZC to the noise inversely proportional to the frequency that is present in the output signal. In particular the load elements can be selected from inductive resistors or silicon resistors or be constituted by resistors of a size selected to optimize the noise inversely proportional to frequency. The invention allows the production of mixers with very good performance at low frequency via a simple micro-electronic process of resistor forming.

Abstract: A direct conversion circuit that not only down-converts the received modulated signal using a down-converting mixer into a baseband signal, but also, after performing a passive low pass filtering to remove higher-order components, performs up-conversion of the baseband signal using an up-converting mixer. Active elements such as highly sensitive amplifiers do not operate on the baseband signal itself, but on the up-converted version of that baseband signal, thereby reducing the 1/f noise introduced by those active elements. The downstream circuitry after the up-conversion may be coupled by intervening capacitors since the downstream circuitry is operating on a higher frequency signal. Accordingly, the DC offset introduced by the downstream active elements is reduced.

Abstract: A frequency conversion apparatus has a high-frequency amplifier for amplifying an input high-frequency signal, a mixer for mixing the output signal of the high-frequency amplifier with a local oscillation signal, a filter for restricting the band of the output signal of the mixer to permit passage of only components within a predetermined band, and a variable filter provided between the high-frequency amplifier and the mixer and having a controllable cut-off frequency. With this configuration, it is possible to reduce back talk at low cost without inviting variation of input return loss characteristics.

Abstract: A frequency converter converts a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency. The frequency converter includes an adder and a switching circuit. The adder adds the first current signal and a reference current signal to output a third current signal. The switching circuit passes only that portion of the third current signal larger in magnitude than a threshold current to output the second current signal.

Abstract: A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.

Abstract: This invention provides a clock generator which is capable of improving modulation accuracy without accompanying an increase in consumption current by steady current when spectrum spread of a clock signal is executed. The phase balanced voltage Vf to be inputted to the voltage control oscillator (VCO) 9 is modulated within a dead band region in which no difference signals Pr, Pr are outputted from the charge pump circuit 7 when a difference in oscillation frequency between an output clock signal fo and a reference clock signal fr is detected. Consequently, the output clock signal fo is changed within the range of a lock frequency in a PLL circuit, so as to execute the spectrum spread of the output clock signal fo while maintaining the lock state of the oscillation frequency in the PLL circuit.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Abstract: The object of the invention is to provide a frequency generator which is composed of an oscillator and a frequency doubler and in which difference in amplitude between differential outputs of the frequency doubler can be equalized at low power consumption without adjustment. To achieve the object, the amplitude of differential outputs of the frequency doubler is detected and the delay time of a variable delay circuit is controlled. Owing to this configuration, in case a frequency of the oscillator varies or in case delay time by the delay circuit used in the frequency doubler varies by process variation and others even if the frequency is fixed, the amplitude of the differential outputs of the frequency doubler can be also equalized in the frequency generator.

Abstract: Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.

Abstract: Circuit comprising a noise suppressing circuitry (40) having an input (42) for a first voltage (VDD) and an output (43) for providing a supply voltage (VDDfiltered). The circuit further comprises a MOSFET-based switch (41) with a MOSFET (MP) being situated in a well, whereby a supply voltage (VDDfiltered) is applied to the well (67). The first voltage (VDD) is a global voltage used elsewhere in the same circuit, and the supply voltage (VDDfiltered) is less-noisy than the first voltage (VDD).

Abstract: A frequency converter converts a first current signal having a first frequency into a second current signal having a second frequency different fro the first frequency. The frequency converter includes an adder and a switching circuit. The adder adds the first current signal and a reference current signal to output a third current signal. The switching circuit passes only that portion of the third current signal larger in magnitude than a threshold current to output the second current signal.

Abstract: Disclosed is a delta-sigma modulated fractional-N PLL frequency synthesizer which performs fractional-N by modulating a divider that divides output frequencies from a voltage controlled oscillator. Fractional part data F from a register is forwarded to a second adder. A first adder adds output from a delta-sigma modulator to output therefrom delayed and inverted by a delay inverter to generate an artificially random bit stream averaging zero. The second adder adds fractional part data F to output from the first adder to generate an artificially random data sequence averaging a value of fractional part data. The generated data sequence is forwarded to the delta-sigma modulator. An adder adds integral part data to output from the delta-sigma modulator. Added output is forwarded to the divider.

Abstract: A charge pump clock for a memory device wherein pump clock signals are generated at an adaptive rate. The circuit of the present invention generates clock edges at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*TD), then clock edges will be generated at a rate that is proportional to the rate of address changes, where TD is approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.

Abstract: A clock generating circuit includes a delay circuit which has input terminals and which delays a signal input from each of the input terminals by a different delay time, and outputs the delayed signal from at least one output terminal, a selective circuit which receives an input clock signal and selectively outputs the clock signal to one of the input terminals of the delay circuit, and a control circuit which switches selective operations of the selective circuit. A modulated clock signal in which the period of the clock signal is increased or decreased is output from the at least one output terminal of the delay circuit such that the control circuit sequentially switches the selective operations of the selective circuit.