Abstract: A power consumption reduction circuit includes a clock frequency downconverting circuit. The clock frequency downconverting circuit downconverts a frequency of a CK signal, which is inputted, when a POR signal inputted is asserted, and outputs the CK signal to an IC selection circuit. In addition, if the POR signal inputted is negated, the clock frequency downconverting circuit outputs the CK signal inputted as it is to the IC selection circuit. A signal outputted from the clock frequency downconverting circuit is supplied to a plurality of ICs through the IC selection circuit.

Abstract: A frequency synthesizer including a divide by R frequency divider providing a first input of a phase detector, a divide by N frequency divider providing a second input of the phase detector, and a voltage control oscillator (VCO) receiving the output of the phase detector and providing an input to the divide by N frequency divider, the VCO output signal being transitioned by varying the frequency division number R. The frequency division number N may also be varied to transition the VCO output signal frequency. A reference oscillator provides an input to the variable R frequency divider and may have its frequency varied to limit resolution error. For greater resolution, multiple frequency synthesizers with divide by R and N frequency dividers having variable frequency division numbers may be connected using mixers to provide a “ratio sum” synthesizer having an output frequency proportional to a sum of N/R ratios.

Abstract: A low-noise, linearized double-balanced active mixer circuit is described, including a first input for a local oscillator (LO), a second input for an intermediate frequency (IF) signal, and an output for a resulting product radio frequency (RF) signal. The mixer circuit also includes a feedback transformer circuit for the purpose of improving the intermodulation (IM) performance. The lossless nature of the feedback topology gives the active mixer a lower noise figure (NF) characteristic than is realizable with conventional methods. The number of active devices is minimized in order to ensure that the mixer attains the lowest possible NF.

Abstract: A digital voltage controlled oscillator is disclosed. The digital voltage controlled oscillator includes an input for receiving input signals representative of a desired frequency. It also includes a pulse generator and a logic circuit. The logic circuit develops an oscillating signal having a predefined waveform and the desired frequency by controlling the energy contained in the pulses output by the pulse generator. The disclosed digital voltage controlled oscillator also includes a capacitor which is charged by the pulses to a voltage that generally varies in accordance with the predefined waveform and the desired frequency.

Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: A low-noise, linearized double-balanced active mixer circuit is described, including a first input for a local oscillator (LO), a second input for an intermediate frequency (IF) signal, and an output for a resulting product radio frequency (RF) signal. The mixer circuit also includes a feedback transformer circuit for the purpose of improving the intermodulation (IM) performance. The lossless nature of the feedback topology gives the active mixer a lower noise figure (NF) characteristic than is realizable with conventional methods. According to a further embodiment, the mixer circuit includes an additional pair of complementary amplifier transistors for the purpose of further improving the IM performance.

Abstract: A system and method of integrating switching amplifiers into systems with low amplitude front-end tuners to eliminate shielding and EMI filtering associated with signals, power and ground. An adaptive frequency programmable pulse frame rate switching amplifier scheme using either look-up tables or appropriate algorithms, ensures by design, the elimination of critical interference frequency generation.

Abstract: A frequency converter, generating an output signal having a frequency of coefficient multiple of a reference clock, comprises a variable oscillator for generating a clock group having phase differences obtained by dividing substantially equally output signal period; a main-phase selector for selecting, from the group, a pair of clocks of desired adjacent phases on a first control signal; a sub-phase selector for selecting, from the pair and a clock phase within the phase difference, the one clock on a second control signal; an operation processor for an operation process by two setting data; a logical controller for generating the control signals on the sub-phase selector clock, the operation processor result, and a phase change control signal; a phase comparator for outputting a phase difference signal between the sub-phase selector and reference clocks; and a controller for controlling the variable oscillator on the phase comparator output.

Abstract: A circuit and method for implementing a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.

Abstract: A mixer of a communication system. The communication system has an antenna, low noise amplifier, a mixer, a local oscillator and an intermediate frequency filter. The mixer has a mixer circuit, a gain amplified circuit, a voltage auto-tracking circuit and a direct current voltage generating circuit. The direct current voltage generating circuit can reduce the output power of the local oscillator, extend the lifetime of the battery used in the mobile communication system, and reduce the distortion of harmonic wave of the local oscillator to reduce the noise figure of the mixer. Using the voltage auto tracking circuit and the gain amplified circuit, the linearity of the mixer is enhanced, and the conversion gain of the mixer is adjusted by varying the load resistors.

Abstract: A frequency converter including a mixer circuit which inputs a local oscillation signal and a radio-frequency input signal modulated for communication of information, and performs frequency conversion. A buffer amplifier is higher than a desired signal frequency band, and has a low-pass passage characteristic of cut-off frequency lower than an adjacent channel carrier frequency.

Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: A selective call radio (300) includes receiver (200). The receiver in turn includes an antenna (202) for receiving a radio signal having a first operating frequency, an amplifier(204) coupled thereto for generating an amplified signal; and a frequency translation circuit (208). The frequency translation circuit includes a selectivity filter (212) and an integrated frequency conversion circuit (216). The selectivity is coupled to the amplified signal for generating a filtered signal. The integrated frequency conversion circuit is coupled to the filtered signal and is incorporated into at least one IC (integrated circuit). The integrated frequency conversion circuit includes an oscillator (220), a divider (224), and a mixer (218). A first input of the mixer is coupled to the filtered signal generated by the selectivity filter. The divider is coupled to the oscillator and its output is coupled to a second input of the mixer.

Abstract: Frequency translation and applications of same are described herein. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same.

Abstract: In an amplifier circuit 20A, outputs of two transistors 23A and 23B are connected in parallel through a power superimposition circuit 27, one ends of drain bias transmission lines 29A and 29B each having a length of &lgr;/4, where &lgr; denotes a signal wavelength, are connected to the outputs of the transistors 23A and 23B, respectively, the ends of the drain bias transmission lines 29A and 29B are connected not only to the capacitors 30A and 30B for signal grounding but also to one ends of bias supply lines 32A ad 32B, respectively, a jumper 34 is connected between the other ends of the bias supply lines 32A and 32B, and the one end of the bias supply line 32B is connected to a drain bias input terminal DB. The drain bias transmission lines 29A and 29B and the power superimposition circuit 27 are each disposed in the shape folded in one direction, and the bias supply lines 32A and 32B each extend in a straight line along a direction perpendicular to the folded direction.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more enable signals in response to a first control signal and a clock signal. The second circuit may be configured to generate an output signal in response to the one or more enable signals and the clock signal. The first circuit is configured to sample a frequency of the clock signal.

Abstract: A method and apparatus for enhancing reliability of a high voltage input/output (I/O) driver/receiver reduces voltage stress on transistors forming part of a logic I/O driver/receiver. The driver/receiver is designed to handle voltages greater than the power supply rails and a bias circuit reduces the voltage stress present on the output stage when a power supply voltage is removed from the circuit. The bias circuit is driven by I/O pin voltage to control a transistor within the I/O logic ladder.

Abstract: A frequency doubler circuit with a 50% duty cycle output includes a two-input XOR or XNOR logic gate having a first input coupled to a digital input signal having a first frequency, and a second input coupled to a replica of the input signal delayed by a quarter of the time period of the input signal. The frequency doubler circuit includes at least two capacitors in series, a constant current generator for charging the capacitors during one of the two half periods of the input signal, and first and second switches controlled in phase opposition by the input signal and by an inverted signal thereof for charging and discharging the capacitors during each period of the input signal. A voltage divider halves the voltage present on the capacitors so that a comparator senses the halved voltage on one of the two capacitors. The comparator provides an output signal to the second input of the logic gate.

Abstract: The present invention relates to an up conversion RF mixer having first differential transistor pair comprising first and second transistors and a second differential transistor pair having third and fourth transistors. The emitters of the first and second transistors are connected to the drain of a fifth transistor and the emitters of the third and fourth transistors are connected to the drain of a sixth transistor. The sources of the fifth and sixth transistors are connected to drains of seventh and eighth transistors, respectively. A local oscillator signal is connected to the bases of the first and second transistors and to the bases of the third and fourth transistors. A first intermediate frequency signal is connected to the gate of the fifth transistor and the gate of the eighth transistor. A second intermediate frequency signal which is the inverse of the first intermediate frequency signal is connected to the gates of the sixth and seventh transistors.

Abstract: An apparatus according to a preferred embodiment of the present invention includes two memories each storing different octants of a sine (or cosine) waveform. The sine and cosine waveforms may be concurrently generated by alternately accessing each memory in succession. It is unnecessary to access one memory concurrently, so that both waveforms may be concurrently generated without requiring either two accesses to the same memory or a doubled memory size.

Abstract: A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node.

Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: A mixer circuit (400) for use with a multi-stage receiver (200) accepts a single ended or differential (i.e. balanced) input (401). A voltage to current converter (402) comprised of a single RF transistor coupled to the input (401) provides a single current node (404) having a current proportional to a received input. A switching network (408) employees a plurality of stages (406). Each stage (406) is connected to the current node (404) and further has a control line (A, B, C, D). A clock signal generator connected to the control lines (A, B, C, D) of the switching network stage (406), generates clock signals having a frequency equal to the frequency of the received RF input signal. The switching network (408) under control of the clock signals switches the current at a frequency y equal to the frequency of the received RF input signal to generate baseband I and Q signals. If the mixer (500) is differential, the balanced signal inputs (520) will be 180° out of phase, one to another.

Abstract: For frequency change, the VCO is controlled through a sub-charge pump circuit to make a determination as to whether or not a difference of dividing data between before and after the change is within a predetermined range. When it is determined that the difference is outside the predetermined range, the loop filer is forcibly charged in a charge time which is determined proportional to the difference in the dividing data, to thereby control an oscillation frequency of the VOC. A large VOC oscillation frequency change can be swiftly realized. Also, while the frequency change circuit is controlling the oscillation frequency, a time constant of the loop filter in the PLL circuit is preferably set at a small value, so that frequency change by the frequency change circuit can be swiftly achieved.

Abstract: A frequency converters used in communications receivers. Such frequency converters can be used for converting a signal from a Radio Frequency (RF) to a low frequency suitable for processing such as demodulation. The inventors have made the unexpected discovery that when the gates of the MESFETs of a double-balanced mixer are left open-circuited and allowed to self-bias, the drop in mixer linearity at high LO power levels is reduced thereby increasing the LO power range of operation. This invention can be used as an improved scale-down mixer as well as an upconverter mixer.

Abstract: A phase noise reduction circuit for reducing phase noise in an input pulse train consisting of pulses which are all of the same length and which, in the absence of phase noise, have a nominal frequency f, includes a DC removal circuit for removing a DC level from the input pulse train, an integrator for integrating the input pulse train after a DC level has been removed therefrom by the DC removal circuit and a comparator for deriving from the integrated pulse train an output pulse train containing periodic transitions at said nominal frequency. The input pulse train may be derived using a monostable circuit.

Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: A system and method for speed-up of the frequency switching time of a circuit, generally a voltage controlled oscillator having an operating frequency controlling input terminal. A first control circuit is coupled to the frequency controlling input terminal for maintaining the operating frequency of the oscillator at its first selected operating frequency. Circuitry is provided which is responsive to a directed change from the first operating frequency of the oscillator to a second different operating frequency of the oscillator to apply a voltage to the input terminal determined by the size of the directed change in the operating frequency and for a predetermined time period. This circuitry includes a switch coupled to the input terminal, a charge pump coupled to the switch and remote from the input terminal and a timer controlling the current output of the charge pump and the switch. The output of the charge pump is a current which is converted to a voltage.

Abstract: A slew rate output circuit includes a switching device connected to an output terminal, a driver circuit connected to the switching device for driving the switching device, and a control circuit connected to the driver circuit for controlling the driver circuit in accordance with an input signal so that, in an initial time period after a change in level of the input signal, the average slew rate is higher than that in a subsequent time period.

Abstract: To provide an analog mixer circuit operating with low power consumption and without needing any BEF for isolating two input signals, an LO signal and an IF signal are supplied to bases of a first transistor (Q1) and a second transistor (Q2) serially connected. A signal of a node (17) where the emitter of the first transistor (Q1) and the collector of the second transistor (Q2) is amplified nonlinearly by a third transistor (Q3) to be output to an output terminal (11), wherefrom an RF signal is extracted by a HPF (18).

Abstract: A semiconductor circuit includes at least first and second field effect transistors. A source electrode of the first field effect transistor is connected to a drain electrode of the second field effect transistor via a first AC current blocking element and is also grounded via a bypass capacitor. A drain electrode of the first field effect transistor is connected to a power supply. A source-drain voltage of the first field effect transistor is equal to or higher than a pinch-off voltage of the first field effect transistor. A source-drain voltage of the second field effect transistor is equal to or higher than a pinch-off voltage of the second field effect transistor.

Abstract: A VCO-mixer structure in accordance with the present invention includes a multi-phase VCO and a multi-phase mixer. The VCO includes a plurality of differential delay cells and the mixer includes a differential amplifying circuit and a combining circuit. The differential amplifying circuit of the multi-phase mixer includes two load resistors coupled to two differential amplifiers, respectively. The combining circuit includes bias transistors, first combining unit and second combining unit coupled to the bias transistors, respectively, and a current source coupled to the first and second combining units. The first combining unit includes a plurality of transistor units, and the second combining unit includes a second plurality of transistor units. Preferably, each of the plurality of transistor units includes a plurality of serially connected transistors, wherein the serially connected transistors are coupled in parallel with the serially connected transistors of the plurality of transistor units.

Abstract: A circuit and method implement a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.

Abstract: Clock generating circuitry comprises a first frequency multiplier for multiplying the frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for furnishing the frequency-multiplied clock, a frequency divider for dividing the frequency of the frequency-multiplied clock furnished by the first frequency multiplier by 227, and for furnishing the frequency-divided clock, and a second frequency multiplier for multiplying the frequency of the frequency-divided clock from the frequency divider by 128, and for furnishing the frequency-multiplied clock. The reference clock can have a frequency of about 4.43 MHz.

Abstract: A phase shifter that may be used in a quadrature modulator or an image suppression mixer. The phase shifter includes a low pass filter that receives an input signal and generates a first carrier signal. A high pass filter also receives the input signal and generates a second carrier signal. A phase difference detection circuit connected to the high and low pass filters receives the first and second carrier signals and generates a control signal based on the phase difference between the carrier signals. The control signal is fed back to at least one of the low pass filter and the high pass filter to compensate for phase errors caused by parasitic capacitance. The phase shifter has a small circuit area and is very accurate, allowing it to be used in communications devices.

Abstract: A frequency converter has both an up-conversion and a down-conversion circuit in a compact circuit design. The converter is operated as an upconverter by activating a first control FET, and is operated as a downconverter by activating a second control FET.

Abstract: A mixing method and mixer structure provide a circuit topology suitable for use in radio receivers, transmitters, tuners, instrumentation systems, telemetry systems, and other systems and devices performing frequency conversion in either homodyne or heterodyne implementations. The inventive mixer may be used for wireless communication devices including radios, cellular telephones, and telemetry systems whether land, sea, airborne, or space based, and whether fixed or mobile. The mixer provides superior intermodulation and harmonic distortion suppression and features excellent conversion loss, noise figure, port match, and port isolation as a result of its circuit topology. The mixer device circuit combines the advantages of series mixing FETs, a triple balanced design using a balanced passive reflection transformer, a precise local oscillator phase splitter, and square wave gate drive having high slew rate signal characteristics to achieve high levels of performance.

Abstract: A frequency translation circuit (10) translates an incoming reference signal (RF.sub.IN) to a lower frequency using a compound mixer circuit (42). The compound mixer circuit (42) has a first mixer circuit (14A) that receives both the incoming reference signal (RF.sub.IN) and a signal generated by a first counter (28A). A second mixer circuit (14X) of the compound mixer circuit (42) receives a signal generated by a second counter (28X) and further translates the signal received from the first mixer circuit (14A) to a lower frequency. Both the first mixer circuit (14A) and the second mixer circuit (14X) generate output signals having a carrier frequency that is lower in frequency by the difference of the two input signals.

Abstract: A linearized double-balanced active mixer circuit is described, including a first input for a local oscillator (LO), a second input for an intermediate frequency (IF) signal, and an output for a resulting product radio frequency (RF) signal. The mixer circuit also includes a feedback circuit, along with a pair of operational amplifiers, for the purpose of improving the intermodulation (IM) performance. According to a further embodiment, the mixer circuit includes a series-shunt feedback amplifier in place of the operational amplifier, and a further embodiment includes an additional pair of transistors to further improve the IM performance. The output of the mixer circuit includes a signal combining circuit, composed of either a network of resistors having two output terminals, or two transformers having a common output terminal.

Abstract: An RF mixer utilizing frequency and bias compensation for improved performance characteristics. The RF mixer receives bias signals that are dependent on V.sub.CC levels to internally balance the local oscillation received and mix the perfectly bias balanced internally generated oscillation signal with the RF input.

Abstract: A frequency translator includes two multipliers which receive one and the same high-frequency signal on first inputs in quadrature with respect to one another, and one and the same low-frequency signal on second inputs also in quadrature with respect to one another. Each multiplier comprises a pair of elements whose capacitance can be varied in a controlled manner, jointly and in opposite senses, connected in parallel. The respective outputs of the two elements of each pair are combined additively, considering their phase opposition, in order to form the outputs of the two multipliers which supply a summer.

Abstract: A mixer circuit (400) for use with a multi-stage receiver (200) accepts a single ended or differential (i.e. balanced) input (401). A voltage to current converter (402) comprised of a single RF transistor coupled to the input (401) provides a single current node (404) having a current proportional to a received input. A switching network (408) employs a plurality of stages (406). Each stage (406) is connected to the current node (404) and further has a control line (A, B, C, D). A clock signal generator connected to the control lines (A, B, C, D) of the switching network stage (406), generates clock signals having a frequency equal to the frequency of the received RF input signal. The switching network (408) under control of the clock signals switches the current at a frequency equal to the frequency of the received RF input signal to generate baseband I and Q signals. If the mixer (500) is differential, the balanced signal inputs (520) will be 180.degree. out of phase, one to another.

Abstract: An oscillation apparatus is provided with a signal input unit for supplying a pulse sequence consisting of pulses sequentially continuously occurred; a state quantity generating unit for generating state quantity having a value which is monotonously increased with the passage of time; a state quantity transition unit for transferring a value of state quantity in the course of generation in said state quantity generating unit to a value changed by a predetermined amount in a varying direction of the value of the state quantity with respect to a present value of the state quantity, whenever one pulse is fed from said signal input unit to said state quantity transition unit; a state quantity reset unit for comparing the present value of the state quantity generated in said state quantity generating unit with a predetermined threshold value, and resetting the present value of the state quantity generated in said state quantity generating unit to a predetermined initial value when the present value reaches the thr

Abstract: A radio frequency synthesizer receives a relatively low frequency input signal and synthesizes from it a high frequency output signal whose frequency can be programmed to change in fine steps, for use e.g. in cordless telephone. The frequency synthesizer includes three linked phase locked loops with a single side band mixer in one embodiment coupling two of the phase locked loops together. This provides an output signal free of in-band frequency spurs within the spacing of two channels. The synthesizer can be integrated in a single chip with a narrowband FM modulation circuit. In spite of using a novel synthesizer to achieve monolithic integration, the user programming interface and control value equations are the industry standard format.

Abstract: A wide dynamic range RF mixer is shown using wide bandgap semiconductors such as SiC, GaN, AlGaN, or Diamond instead of conventional narrow bandgap semiconductors. The use of wide bandgap semiconductors will permit RF mixers to operate in higher RF environments, to be less susceptible to out-of-band jamming and interference, and to be more effective in receiving weak RF signals in the presence of strong unwanted signals.

Abstract: A radio comprising an FET mixing device for multiplying a first-frequency signal with a second frequency signal to generate a third frequency analog mixer output signal. A local oscillator input port receives a periodic sinusoidal local oscillator signal at a local oscillator frequency from an external local oscillator source. A drive circuit generates a substantially square-wave two-voltage level switching signal for driving said mixing device. An analog-to-digital converter generates a digital representation of said third frequency analog mixer output signal.

Abstract: A frequency control circuit for an oscillator and a method therefor are disclosed and which frequency control circuit includes a flash cell having a cell transistor, a switching unit for outputting a first voltage to the flash cell in the program mode in accordance with an enable signal and outputting a second voltage in the read mode, a write driver for outputting a program voltage to the flash cell in the program mode in accordance with the enable signal, a bias unit for supplying a current to the flash cell in the read mode in accordance with the enable signal and generating a frequency control voltage which is proportional to a threshold voltage of the flash cell, and an oscillator for varying the frequency in accordance with the thusly generated frequency control voltage.

Abstract: It is an object of the present invention to reduce the amount of spurious noise generated by an emission line spectrum of a signal propagating around the PLL of a PLL frequency synthesizer carrying out digital-signal processing.In order to achieve the object described above, the present invention provides a PLL frequency synthesizer with the following configuration.In a PLL frequency synthesizer having a charge-pump circuit, a waveform converter is provided at a stage behind the charge-pump circuit. The waveform converter converts the voltage waveform on a time axis of a rectangular wave output by the charge-pump circuit into a waveform which: is symmetrical with respect to a predetermined point of time; oscillates so as to have no direct-current component; and has a maximum value of the absolute values of maximums of wave heights thereof located at the center wherein the absolute value decreases uniformly as the wave height is separated farther away from the center.

Abstract: A clock generating system used to generate a clock signal which compensates for chip operating conditions. The system includes a delay line oscillator and a reference clock which determines the actual propagation time of delay elements on the chip. A clock generator which includes a number of serially connected delay units uses this information to generate a clock signal for the chip logic functions. The output clock rums the chip logic functions at the proper frequency for the current chip conditions.

Abstract: A mixer circuit (230) comprises a double balanced mixer (370) including a first pair of transistors (Q3, Q4) and a second pair of transistors (Q5, Q6) and a differential amplifier (330) including a pair of transistors (Q1, Q2) coupled to a first reference voltage (302). A coupling element (C3) is inserted between a common emitter node (391) of the first pair of transistors (Q3, Q4) of the double balanced mixer (370) and the output node of one of the pair of transistors (Q1) of the RF input stage (330), and a coupling element (C4) is inserted between a common emitter node (392) of the second pair of transistors (Q5, Q6) of the double balanced mixer (370) and the output node of the other pair of transistors (Q2) of the differential amplifier (330).