Abstract: A frequency converter comprising a variable gain amplifier which amplifies the local oscillation signal according to a gain control signal and outputs an amplified local signal, an even harmonic mixer which is supplied with an input signal and an amplified local oscillation signal and outputs an output signal whose frequency is a sum of a first frequency of the input signal and a second frequency of two or more even numbered times a frequency of the amplified local oscillation signal, an amplitude detector which is supplied with the amplified local oscillation signal and outputs a direct current signal having an amplitude corresponding to an amplitude of the amplified local oscillation signal, and a comparator which compares the direct current signal of the amplitude detector with the reference direct current signal to generate an output signal as the gain control signal.

Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Abstract: A multiple PLL oscillator for oscillating and outputting a plurality of frequencies having a predetermined step frequency, comprising a first and a second reference frequency sources, a switch for selecting the ore of outputs of the first and the second reference frequency sources alternatively and at predetermined time interval, and a PLL frequency synthesizer generating a millimeter wave oscillation output corresponding to each of the first and second reference frequency sources.

Abstract: A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.

Abstract: A direct conversion type of frequency transposition device includes a transconductor block receiving the input signal and a current switching block connected to the output from the device. At least the common mode (Iif1+Iif2) is servocontrolled to static output currents from the frequency transposition device on a current proportional to a reference current (Iref) and independent of the static output currents from the transconductor block.

Abstract: A frequency and phase locked loop having improved performance. The loop measures both frequency and phase of a modulated signal to supply a carrier for demodulation of a quadrature amplitude modulated signal (QAM) signal and for many other applications. The addition of the frequency measurement and the use of finite impulse response filters instead of infinite impulse response filters of a phase locked loop permit the loop to lock to the carrier much more rapidly and with a larger offset.

Abstract: A semiconductor integrated circuit chip includes a replica circuit for delaying a reference clock signal, a delay detector for controlling a delay time of the replica circuit such that the delay time of replica circuit becomes one-fourth the period of the reference clock signal, and an EX-OR gate that receives the reference clock signal and an output clock signal from replica circuit for supplying to a logic circuit an internal clock signal that is obtained by multiplying the reference clock signal by two. Thus, the consumed power can be kept small in comparison with the conventional example in which an internal clock signal is propagated on a clock line.

Abstract: A frequency conversion apparatus has a high-frequency amplifier for amplifying an input high-frequency signal, a mixer for mixing the output signal of the high-frequency amplifier with a local oscillation signal, a filter for restricting the band of the output signal of the mixer to permit passage of only components within a predetermined band, and a variable filter provided between the high-frequency amplifier and the mixer and having a controllable cut-off frequency. With this configuration, it is possible to reduce back talk at low cost without inviting variation of input return loss characteristics.

Abstract: A clock generation circuit and device are disclosed for reading/writing information from to/an information carrier. The clock generation circuit includes a frequency divider for generating a first intermediate clock signal from an input clock signal. A first logical unit combines the input clock signal and the intermediate clock signal. The circuit further includes a clocked bistable unit having a clock input coupled to an output of the first logical unit, and a data input and a data output, and a second logical unit having a selection input for receiving a synchronization signal from a synchronization module having an input for receiving a reference clock signal. The synchronization signal controls selection between a feedback mode and a reset mode. In the feedback mode, the second logical unit logically inversely couples the data input to the data output, and in the reset mode the second logical unit provides a reset value to the data input. The data output provides the output clock signal.

Abstract: A frequency correction circuit for accurately correcting clock signals of an oscillating frequency with a simplified configuration without adjusting an oscillator circuit generating the oscillating frequency. A count adjuster of a time-base counter (TBC) receives a delay control signal and a clock signal. The count adjuster includes an inverter and an AND gate. The inverter is responsive to the delay control signal and develops an output signal, while the AND gate receives the clock signal. During the high level period of the delay control signal, the AND gate sends out the clock signal, from which one clock has been erased, as a clock signal of the initial stage T-type flip-flop of a clock frequency divider, which then produces an output signal, from which deviations have been removed.

Abstract: A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set at the highest permissible speed existing at the time of system reset.

Abstract: A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

Abstract: A double balanced mixer circuit 10 receives an input signal (RFIN) at first input terminals (14), supplying that signal to the primary side of a transformer (12). The secondary side of the transformer (12) is coupled to the bases of transistors (18 and 26) that supply the tail currents to a pair of differential transistors. The center tap of transformer (12) receives a voltage (VBIAS) that keeps the transistors (18 and 26) biased in their linear regions. A capacitor (16) provides an AC ground at the center tap point of the transformer (12). The first differential transistor pair (20 and 22) and the second differential transistor pair (28 and 30) receive a differential signal (LO) at second input terminals 15. A differential signal IFOUT down-converted in frequency from the RF frequency range to the IF frequency range is supplied at output terminals (34).

Abstract: A frequency conversion circuit for changing a frequency of an input signal to obtain an output signal, includes: a sum holding unit holding a sum; an integrating unit updating the sum by changing the sum by a natural number a in one direction at each input of a first predetermined signal based on the input signal; and an output signal generating unit outputting a second predetermined signal as the output signal at each time at which the sum has gone over (b*N+c), where N is an integer, c is a constant integer and b is a natural number equal to or larger than a.

Abstract: In a circuit for converting an input signal Datal of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Abstract: A micro-controller adjustably provides a scanning frequency for operating a driver for an ultrasonic device. The frequency is adjusted within a defined range until an acknowledgement signal is provided to the micro-controller to lock a currently selected frequency as the operating frequency. An indicator indicates when a frequency has been selected outside of the defined range. The device is preferably implemented as a complex programmable logic device (CPLD).

Abstract: A multi-channel synchronous voltage-to-frequency converter (SVFC) realized in an integrated semiconductor circuit. The multi-channel SVFC having an operational amplifier adapted to receive an analog data signal to be converted and a reset signal, the operational amplifier integrating the sum of the analog signal and the reset signal and generating an output signal as a function of the integrated sum; a comparator coupled to receive the integrated sum and a reference level signal, the comparator outputting a logic level signal as a function of the received reference level signal; a digital logic circuit in response to an external clock signal, the digital logic circuit receiving the logic level signal and generating a reset control signal and a frequency output pulse as a function of the logic level signal; and a reset source switch receiving the reset control signal and outputting the reset signal.

Abstract: Radio system including mixer device and switching circuit and method having switching signal feedback control for enhanced dynamic range and performance. Radio apparatus including: local oscillator input port for receiving periodic sinusoidal local oscillator signal; drive circuit for generating a substantially square-wave two-voltage level switching signal including: phase splitter circuit, voltage potential isolation circuit, and square wave signal generation circuit; FET mixing device; input/output signal separation circuit; analog-to-digital converter; and feedback control circuit. Radio tuner apparatus including low-band signal processing circuit; high-band signal processing circuit including first mixer circuit operating as an up-frequency converter, amplifier circuit, second mixer circuit operating as a down-frequency converter, and feedback control circuit for adjusting a duty cycle of a mixer switching device; signal combining circuit and output processing circuit.

Abstract: A four-quadrant multiplier for mixing RF signals comprises two differential amplifiers respectively connected as a load of a third differential amplifier. Both the negative feedback and the load of the third differential amplifier can be altered. Changing the negative feedback permits adjustment of the linearity range of the four-quadrant multiplier.

Abstract: The numerically controlled oscillator (8) is mounted in particular in a radiofrequency signal receiver which further includes means (3) for receiving and shaping the radiofrequency signals, a correlation stage (4) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage (12) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage (12) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: A compact frequency multiplier can perform high-degree frequency multiplication and can be incorporated in a wireless device. The frequency multiplier includes an input terminal for inputting an input signal, a first resonant circuit resonating with the frequency &ohgr; of the input signal, a second resonant circuit and an idler circuit, which resonate with the frequency n·&ohgr; that is, n times the frequency of the input signal, a variable reactor such as a varactor diode, coupling-adjusting capacitors, a bias resistor, and an output terminal for outputting multiplied output signals. In one embodiment, the frequency multiplier is a current-excitation type. The first resonant circuit and the second resonant circuit, each of which is constituted of an LC series resonant circuit, are connected in series between the input terminal and the output terminal.

Abstract: A clock divider circuit producing 0° and 90° outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a pair of cross-coupled circuits. The clock divider circuit may produce a first output clock signal and a second output clock signal that is phase shifted a positive 90° with respect to the first output clock signal. The operation of the circuit may be responsive only to the input clock signal. In other words, the circuit may not require a reset signal to operate in a deterministic fashion.

Abstract: A prescaler (200) includes a first frequency divider (204, 206) configured to receive an input signal at an input frequency. The prescaler further includes a phase rotator (208) coupled to the first frequency divider to produce a plurality of signal phases in response to the input signal. A frequency control circuit (214) is configured as a one-hot decoder to select one signal phase of the plurality of signal phases. The one-hot decoder provides maximum speed of operation of the prescaler by eliminating decoding of the feedback signal.

Abstract: The semiconductor integrated circuit capable of reducing the length of time required for clock switching is provided. The semiconductor integrated circuit includes a clock generation control circuit which is provided with a register capable of writing and reading specific data, and generates a frequency divided clock by inputting a reference clock with the timing of a clock frequency division setting signal. A clock control circuit 8 constituting this semiconductor integrated circuit comprises a status shift circuit 236 that controls clock frequency division/switching, a switching timing generation circuit that measures the timing with which a clock switch is made and a selection switching circuit that makes a switch between the reference clock and the frequency divided clock.

Abstract: A clock modulation circuit modulates the frequency of a clock signal to generate a modulated clock signal. A wait requesting signal receives frequency information indicating the frequency of the modulated clock signal and, when the frequency information indicates a frequency higher than a reference frequency, generates a wait requesting signal to an external bus interface. Since an optimum wait cycle is inserted to the external bus interface according to a change of the frequency of the modulated clock signal, needless wait cycle can be prevented from being inserted to the external bus interface. As a result of this, it is possible to disperse the peak of radiated noise which is caused by the clock signal and to reduce electromagnetic interference, without decreasing performance of a system. Namely, it can serve both market needs for reducing noise and speeding up.

Abstract: An analog multiplier or mixer that mixes a signal fc with a square wave local oscillator improves heterodyning operation of a circuit. In various square wave analog multiplier or mixer embodiments, heterodyning performance is improved in noise reduction, saturation performance, linearity, and other measures by adding a DC current path in parallel to a signal current path of the multiplier or mixer. The parasitic capacitances, noise, and nonlinearity problems in a heterodyning circuit are solved by adding a path to a square wave mixer for carrying the signal current and the DC current on different paths. An apparatus includes a circuit coupled between a first voltage reference and a second voltage reference. The circuit includes a first square wave oscillator branch and a second square wave oscillator branch. The first square wave oscillator branch is driven by a square wave oscillator signal and the second square wave oscillator branch is driven by an inverse of the square wave oscillator signal.

Abstract: A mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, a biasing network of the output stage including, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.

Abstract: A method for converting the frequency of an electrical signal, where an input signal is received, a first local signal and a second local signal of a different phase than the first local signal, are generated. A first product signal is obtained by mixing said input signal with the first local signal and a second product signal is obtained by mixing said input signal with the second local signal. The first and second product signals are combined together. The mixing of the input signal with the first local signal and the mixing of the input signal with the second local signal occurs in alternating time periods. The same mixing element is used for processing two or more branches in order to avoid imbalance in the mixed signals due to usage of separate, mismatching, mixing elements. The invention also relates to radio devices implementing the method described above.

Abstract: A system including a component (e.g., a processor) with a clock and a thermal management controller that monitors a temperature in the system. The thermal management controller varies the component between different performance states (e.g., cycles the processor between a high and a low performance state) when an over-temperature condition is detected. The thermal management controller further throttles the clock of the component while in the low performance state until the over-temperature condition is removed.

Abstract: A frequency converter configured to convert a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency is disclosed, which comprises an adder configured to add the first current signal and a predetermined reference current signal to output a third current signal corresponding to the sum of the first current signal and the reference current signal, and a switching circuit configured to pass only that portion of the third current signal which is larger in magnitude than a threshold current to output the second current signal.

Abstract: The output (&thgr;2) of a digital adder (13) before being held by a first data holding circuit (14), a first reference value (D1) and a second reference value (D2) are compared, respectively, by a first data comparator (15) and a second data comparator (16), to thereby change one cycle of the output control of the pulse train fout from four cycles (T1-T4) to two cycles (T1-T2) of the reference clock. Further, by comparing the output (&thgr;1) of the first data holding circuit (14) and the first reference value (D1) by a third data comparator (19), the latch timing of the overflow signal is changed from T4 to T1.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

Abstract: A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node.

Abstract: An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier.

Abstract: An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, the selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the usual operation.

Abstract: A clock modulator spreads the frequency spectrum of an input clock to generate an output clock. A capacitor is connected to an intermediate clock node by a load-switching transistor. When the transistor is turned on, the capacitor increases the loading on the intermediate clock node, increasing delay. When the transistor is turned off, the delay is reduced. Output clock cycle periods are extended when delay is added, and reduced when the transistor turns off. A counter or sequencer is clocked by the input clock and drives the load-switching transistor. The transistor is turned on and off for alternate cycles when the counter is a toggle flip-flop, spreading the frequency over two frequencies every two clock cycles. Two capacitors of different sizes, connected to the intermediate clock node by two transistors, can be switched by a 2-bit sequencer, spreading the output clock over 7 frequencies every 7 clock cycles.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: A frequency synthesizer includes a direct digital synthesizer (DDS), a digital-to-analog converter for converting the output of the DDS to a DDS output signal, a first bandpass filter for filtering the DDS output signal, a single side band mixer for mixing the filtered DDS output signal with a mixing frequency signal, a divider for dividing the mixer output, a second bandpass filter for filtering the mixer output, and a phase lock loop for turning the filtered mixer output into a signal of the desired frequency. This frequency synthesizer combines the high resolution of a DDS with high bandwidth and low noise.

Abstract: A clock modulation circuit modulates the frequency of a clock signal to generate a modulated clock signal. A wait requesting signal receives frequency information indicating the frequency of the modulated clock signal and, when the frequency information indicates a frequency higher than a reference frequency, generates a wait requesting signal to an external bus interface. Since an optimum wait cycle is inserted to the external bus interface according to a change of the frequency of the modulated clock signal, needless wait cycle can be prevented from being inserted to the external bus interface. As a result of this, it is possible to disperse the peak of radiated noise which is caused by the clock signal and to reduce electromagnetic interference, without decreasing performance of a system. Namely, it can serve both market needs for reducing noise and speeding up.

Abstract: A frequency converter circuit and method is disclosed. The circuit may comprise: two pairs of differential amplifying transistors; two current mirrors, wherein each of the two current mirrors is operable to feed a respective one of the two pairs of differential amplifying transistors; a further pair of differential amplifying transistors, wherein each transistor of the further pair of differential amplifying transistors is operable to feed a repective one of the two current mirrors; and a pair of bypass transistors connected in parallel with a controlling side of the two current mirrors, wherein the bypass transistors reduce a direct current component of a current being mirrored.

Abstract: The present invention provides a circuit for adjusting operating frequency of a chip, and comprises an oscillator, a controlling circuit, and a voltage adjusting circuit. The oscillator is coupled to the chip for outputting a testing clock signal according to a voltage signal. The controlling circuit is coupled to the oscillator for comparing the testing clock signal and a predetermined clock frequency, then outputting a voltage controlling signal. The voltage adjusting circuit is coupled to the controlling circuit for adjusting the voltage value of the voltage signal according to the voltage controlling signal.

Abstract: In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.

Abstract: A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set at the highest permissible speed existing at the time of system reset.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

Abstract: A mixer circuit having a high conversion gain which is excellent in linearity comprises an amplifier (1A) for amplifying one of two signals to be mixed with each other. The amplifier (1A) comprises a low-pass filter (14) not damping an input voltage (v1) of a frequency (f1) on a negative feedback circuit for its output. Due to the low-pass filter (14), it is possible to reduce harmonics by increasing the feedback amount as the frequency is increased.

Abstract: It is intended to provide a compact circuit configuration used for a frequency multiplier device, suitable to selectively output among a plurality of multiplied frequencies, with less power consumption. The frequency multiplier device uses an input frequency signal f and an output multiplied signal nf to form original signals a and c, as well as phase shifted signals b and d that are phase shifted to ±&pgr;/2 from the original signals a and c, the signals are mixed in a mixer circuits 16 and 17 and summed in a summing amplifier 18 to generate an output frequency signal fOUT. The phase inverter circuit (differential amplifier circuit) 14 and selector circuit (SEL1) 33) controls the phase inversion of one of signals to selectively output one of mixed frequencies (n±1)f as the output frequency signal fOUT.

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

Abstract: In an amplifier circuit 20A, outputs of two transistors 23A and 23B are connected in parallel through a power superimposition circuit 27, one ends of drain bias transmission lines 29A and 29B each having a length of &lgr;/4, where &lgr; denotes a signal wavelength, are connected to the outputs of the transistors 23A and 23B, respectively, the ends of the drain bias transmission lines 29A and 29B are connected not only to the capacitors 30A and 30B for signal grounding but also to one ends of bias supply lines 32A ad 32B, respectively, a jumper 34 is connected between the other ends of the bias supply lines 32A and 32B, and the one end of the bias supply line 32B is connected to a drain bias input terminal DB. The drain bias transmission lines 29A and 29B and the power superimposition circuit 27 are each disposed in the shape folded in one direction, and the bias supply lines 32A and 32B each extend in a straight line along a direction perpendicular to the folded direction.

Abstract: A drive control circuit of a charged pump circuit has a power source voltage detecting circuit for detecting a power source voltage, a control circuit for changing the number of the drive steps of the charged pump circuit in accordance with the detected output of the power source voltage detecting circuit, and a by-pass circuit for allowing an output at the last step to be by-passed towards an output side of the drive steps in accordance with a change in the number of drive steps of the charged pump circuit.