Abstract: The present invention relates to a system for synchronising slave and master timing, comprising a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to the slave timing, and a master phase detector and lock circuit for comparing relative phases of the master and slave timing and in response generating and applying delay adjust signals to the phase adjust circuit at a dynamically adjusted rate which is related to the relative phase in order to synchronise the slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of the slave and master timing.

Abstract: A apparatus to provide a direct modulation transmitter having high dynamic range and low distortion using signal processing at a first frequency level for a signal to be transmitted and increasing frequency to transmission frequency in a manner to avoid distortion and utilizing a squaring function in up-converting basic processing signal.

Abstract: A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.

Abstract: A frequency converter comprising a variable gain amplifier which amplifies the local oscillation signal according to a gain control signal and outputs an amplified local signal, an even harmonic mixer which is supplied with an input signal and an amplified local oscillation signal and outputs an output signal whose frequency is a sum of a first frequency of the input signal and a second frequency of two or more even numbered times a frequency of the amplified local oscillation signal, an amplitude detector which is supplied with the amplified local oscillation signal and outputs a direct current signal having an amplitude corresponding to an amplitude of the amplified local oscillation signal, and a comparator which compares the direct current signal of the amplitude detector with the reference direct current signal to generate an output signal as the gain control signal.

Abstract: Method and system are disclosed for providing an improved linearity Gilbert mixer. The Gilbert mixer of the present invention includes a conventional mixer core coupled to a high linearity, multistage amplifier. The multistage amplifier includes two or more transistor stages connected together in a global feedback arrangement. The global feedback provides a greater loop gain for the amplifier than the local feedback arrangement, thereby increasing the linearity of the amplifier. In addition, having more than one transistor stage in the amplifier serves to increase the isolation of the RF input signal from the LO input signal. Furthermore, by providing parallel output stages in the multistage amplifier, several mixer cores may be driven from the same source while sharing the feedback mechanism.

Abstract: An integrated semiconductor image-rejection mixer having high linearity and high gain. In addition to the components of a classic image-rejection architecture, the present mixer has a high-frequency current-diverting stage that permits the operation of the output stage with high conversion gain and sufficient headroom for good linearity, even in cases where the supply voltage is relatively low (such as 3 V). The conversion gain of the mixer and its image-rejection performance can be changed by changing the load resistances and the elements of the output polyphase network, with minor effects on linearity and no change in power consumption or DC levels. The power consumption of the image-rejection mixer is low because no additional DC current is required for buffers or amplifier stages.

Abstract: A frequency conversion circuit arrangement is disclosed providing a complex output signal at its output. The circuit comprises two frequency mixers that are driven, on the one hand, by an input signal and, on the other hand, by a feedback signal. In this case, the feedback signal is the frequency-divided output signal and has been broken down into an in-phase component and a quadrature component. The frequency conversion circuit provides a signal at an output frequency in a manner independent of production tolerances and accurately in terms of frequency, said signal being in the form of an IQ signal and additionally being decoupled, in terms of frequency, from the input signal. The frequency conversion circuit is therefore particularly well suited to use in mobile radio transceivers.

Abstract: A method is disclosed for operating a radio frequency transmitter chain component, as is a radio frequency transmitter chain component that operates in accordance with the method. The method includes receiving an input signal to be mixed with a signal output from an oscillator, where the input signal is received through an operational amplifier. The method further includes applying an output of the operational amplifier to an input of a mixing circuit, rectifying the input signal to produce a rectified input signal and controlling a common-mode output voltage of the operational amplifier with the rectified input signal. This process varies the power consumption of the component in a manner that is proportional to a value of the input signal. A further step couples a mixer output signal to an input of a VGA. The component may include both the mixer and the VGA. In the preferred embodiment the input signal and the mixer output signal are differential signals.

Abstract: The mixer circuit is a singled ended input to a double balanced high dynamic range mixer with only two base-emitter junctions across the supply. It provides for the use of bondwires to off chip ground as DC block and DC feed elements. The single ended input and differential output balanced mixer is well suited for the input stage of an integrated radio receiver—off chip circuitry is usually single ended, but on chip circuits are usually differential. No off chip differential RF circuits or baluns are required which reduces off chip component count and improves radio performance. The mixer circuit has lower LO drive requirements because of the DC coupled LO port. This results in better radio performance and a smaller die area because of the DC coupled IF port.

Abstract: An active inductor includes bipolar transistors T1, T2, T3 and TD (TD being arranged in diode), where T1's emitter is connected to an output port and to T2's collector. T2's base is connected to a first voltage line and between two connected capacitors. T2's emitter is connected to T3's collecter. An end of one capacitor is connected to T1's base and to a second voltage line. An end of the other capacitor is connected to T3's emitter and to a third voltage line. T1's collector is connected to a fourth voltage line and to TM's collecter, which is connected to TM's base. TM's emitter is electrically connected to T3's base. Preferably, the transistors T1–T3 and TD are Silicon based, and the active inductor is fabricated on a single substrate comprising Silicon. The active inductor is incorporated into adaptive oscillators and amplifiers and an improved transceiver.

Abstract: An apparatus comprising an amplifier circuit, a tuning circuit and a mixer circuit. The amplifier circuit may be configured to generate an output signal at a first node in response to an input signal received through a second node. A tuning circuit may be (i) coupled between said second node of the amplifier circuit and third node and (ii) configured to adjust an impedance presented to the third node in response to a tuning voltage. A mixer circuit may have a center tap coupled to the third node.

Abstract: Frequency translation and applications of same are described herein. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same.

Abstract: The phase continuous synthesizer and method generate a relatively wideband swept frequency signal with the use of a first generator for generating a first swept frequency signal, and a second generator successively switching between different frequency signals while creating undesired phase discontinuities during switching. A mixer is connected to the first and second generators for mixing the first swept frequency signal and the successively switched different frequency signals to produce the relatively wideband swept frequency signal, and a phase coasting unit is connected downstream of the mixer to reduce the undesired phase discontinuities created during switching in the relatively wideband swept frequency signal.

Abstract: Disclosed is a quadrature signal generator for generating an in-phase signal and a quadrature-phase signal, which is capable of generating a quadrature signal having the same frequency as a differential oscillating frequency, using a feedback control system.

Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Abstract: A multiplier circuit has an analog multiplier with two signal inputs. A respective switching device is connected to each one of the two signal inputs of the analog multiplier for periodically reversing the polarity of the input voltages. A clock signal that can be fed to the switching devices has a changeover frequency that is preferably greater than or equal to twice the useful signal frequency. This suppresses offset-governed crosstalk of the input signals to the output of the analog multiplier. This principle can also be employed in quadricorrelators.

Abstract: A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.

Abstract: An RF transmitter having two digital to RF-conversion devices that combine the D/A conversion function and the upconversion function by a RF-carrier or IF-signal. The device comprises a plurality of parallel unit cells, each of which is a mixer cell type converter having a differential data switch section connected in series to a differential LO-switch pair. The differential LO-switch is further connected in series to a current source. Each unit cell is adapted to receive a control voltage indicative of a data signal value.

Abstract: A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the programmable mixer are set to zero, or to a known state and the local oscillator is set to a calibration frequency. Then, one of a plurality of known calibration states of the programmable mixer is entered and the local oscillator feedthrough is measured. For each of a plurality of operating states an amplified output of the programmable mixer is measured. In one operation, the state of the programmable mixer in which the programmable mixer operates during a next operation phase is the state that produces minimal local oscillator feedthrough. In another operation, operation continues until a state is found that produces a local oscillation feedthrough that meets an operating criteria and that state is used during the next operation phase.

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.

Abstract: By implementing the sampling process at an AC ground node, rather than at a signal side, and adding a gated transistor (610 and 620) in the signal path, the present invention reduces the interdependency between gain and linearity in a switched capacitor mixer circuit, supplies higher power without sacrificing area and simplifies the implementation of the RF switch. Charge boosting circuitry (630) allows a reduction in the effective size of a series switch (610 and 620) that follows a transconductance element (115).

Abstract: A frequency converter configured to convert a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency is disclosed, which comprises an adder configured to add the first current signal and a predetermined reference current signal to output a third current signal corresponding to the sum of the first current signal and the reference current signal, and a switching circuit configured to pass only that portion of the third current signal which is larger in magnitude than a threshold current to output the second current signal.

Abstract: A mixer circuit is provided for receiving first and second input signals to be mixed and for producing a mixed output signal. The mixer circuit comprises a pair of switching transistors each of which having first, second and third terminals. The mixer circuit further comprises a single ended input connected to the first terminals of the pair of switching transistors, a local oscillator input connected to the second terminals of the pair of switching transistors for controlling the switching of the transistors, a serial capacitor connected in serial connection between the single ended input and the first terminals of the pair of switching transistors, a pair of output capacitors each of which being connected to a third terminal of the pair of switching transistors. Said third terminals of said pair of switching transistors forming an output port. The mixer circuit provides a mixer schematic with improved noise performance.

Abstract: A digital to RF-conversion device that combines the D/A conversion function and the upconversion function by a RF-carrier or IF-signal. The device comprises a plurality of parallel unit cells, each of which is a mixer cell type converter having a differential data switch section connected in series to a differential LO-switch pair. The differential LO-switch is further connected in series to a current source. Each unit cell is adapted to receive a control voltage indicative of a data signal value.

Abstract: One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay signal having a first period and a first phase, and at least some falling edges of the timing signal are based on edges of a second delay signal having a second period that is substantially the same as the first period, and a second phase that is different from the first phase. Another embodiment of the invention is directed to a programmable clock synthesizer comprising an edge-triggered circuit that receives a rising edge delay signal and a falling edge delay signal, wherein the edge-triggered circuit is adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.

Abstract: A digitally controlled frequency synthesizer has a first direct digital synthesizer that generates a first phase-coherent, time-varying frequency, and a second direct digital synthesizer that generates an offset frequency waveform. A plurality of cascaded frequency converters successively combine the offset frequency waveform with a reference frequency waveform to produce a plurality of waveforms having respectively different frequencies. A switch switches between the plurality of waveforms produced by the cascaded frequency converters to realize a second waveform. The operation of the second direct digital synthesizer is controlled so as to maintain phase continuity between respective ones of the plurality of waveforms contained in the second waveform as output by the switch. A mixer multiplies the first waveform by the second waveform to produce a time-varying output frequency.

Abstract: A memory system includes a memory device that includes an active termination circuit. The memory system further includes a controller circuit that includes a frequency control circuit that is configured to modulate a system clock between a first frequency value and a second frequency value, greater than the first frequency value, responsive to a control signal. The controller circuit is further configured to determine an active termination value for the active termination circuit responsive to the system clock at the first frequency value, and to apply commands to the memory device responsive to the system clock at the second frequency value.

Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit.

Abstract: A circuit configuration for mixing a differential desired signal with a differential local oscillator signal includes two difference amplifiers which are controllable on the input side by the desired signal and cross-coupled on the output side. Currents flowing through the difference amplifiers are switched by the components of the local oscillator signal in alternation. The circuit makes a lower supply voltage possible, given the presence of only two transistor levels.

Abstract: A current-reusing bleeding mixer capable of providing a higher conversion gain, linearity and lower noise figure employing a field-effect transistor includes a first to a fourth transistor and a first and a second load element. The first transistor amplifies a radio frequency (RF) signal. The second and the third transistor, each connected to the first transistor, receive a balanced local oscillator (LO) signal to mix it with the RF signal. The first and the second load element are connected between a supply voltage source and the second transistor and between the supply voltage source and the third transistor, respectively. The fourth transistor, connected between the supply voltage source and the first transistor, amplifies the RF signal and bleeds a current from the supply voltage source.

Abstract: A frequency multiplier circuit is provided that does not rely on filtering to remove unwanted harmonics and spurious content. In one implementation, a frequency doubler comprises a first rectifier doubler stage adapted to receive a first input signal having a first frequency and output a first rectified signal having multiple harmonics; a second rectifier doubler stage adapted to receive a second input signal having the first frequency and offset in phase from the first input signal and to output a second rectified signal, which has the multiple harmonics and is offset in phase from the first rectified signal; and a differential amplifier stage adapted to sum the first and second rectified signals to produce an output signal including a desired output harmonic having a frequency that is double the first frequency. The summing results in the substantial cancellation of unwanted output harmonics in the output signal.

Abstract: A surface mount, even harmonic mixer is preferably used in point-to-multipoint millimeter wave transceivers. The mixer includes an anti-parallel series arrangement of diodes in one or more ring quads to increase the input 1 dB compression point and third-order input intercept point (IP3), while maintaining the benefits inherent with even harmonic mixing.

Abstract: The present invention provides a frequency conversion circuit capable of reducing current without impairing high frequency characteristics. A local oscillator amplifier is formed of a first field effect transistor. A source thereof is grounded by a first capacitor in terms of high frequency, and a gate thereof is connected to one end of each of first and second resistors. The other end of the first resistor is grounded, and the other end of the second resistor is connected to a voltage supply terminal. An intermediate frequency amplifier is formed of a second field effect transistor. A source thereof is grounded through a third resistor and a second capacitor that are connected in parallel with each other. A drain thereof is connected to an intermediate frequency signal output terminal through a third capacitor and an intermediate frequency output matching circuit. The source of the first field effect transistor and the drain of the second field effect transistor are connected through an AC blocking circuit.

Abstract: Methods and apparatuses for generating a synchronous digital output signal stream from two digital input signal streams. In one aspect of the present invention, a method to generate a digital output signal stream from two digital input signal streams includes: detecting a first transition edge in a first digital input signal stream; and generating a third transition edge in a digital output signal stream. The third transition edge corresponds to the first transition edge; and the third transition edge is synchronized substantially with a second transition edge in a second digital input signal stream. In one example according to this aspect, a third digital signal stream is generated from synchronizing substantially transition edges of the first digital input signal stream with transition edges of the second digital input signal streams; and the first transition edge is detected using the third digital signal stream (e.g.

Abstract: A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.

Abstract: A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.

Abstract: A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further determine whether the falling edge of the output clock should be triggered by the rising or the falling edge of the falling edge of the input clock signal. The counter may be implemented as a M/N:D counter in which a phase accumulator is compared to predetermined values to select the rising and falling edges of the output clock signal. In a default condition, the rising and falling edges of the output clock signal are triggered by rising edges of the input clock signal. However, if the accumulated phase value is greater than or equal to M/2 and less than M, an overriding signal will trigger the rising edge of the output clock based on the falling edge of the previous input clock cycle.

Abstract: To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to the input signal (1, 2) by a quarter of the latter's cycle period is generated and the output signal (11) is then generated as the difference between the rectified input signal (1, 2) and the rectified delayed signal (3, 4). The input signal (1, 2) and the delayed signal (3, 4) are advantageously rectified by using differential signals each comprising a positive component signal (1, 3) and a negative component signal (2, 4). A respective one of two transistors connected in parallel is driven by a positive component signal (1, 3) and a negative component signal (2, 4) in such a way that a positive half-wave causes the relevant transistor (5-8) to conduct and the relevant transistor (5-8) blocks in a negative half-wave.

Abstract: The output (&thgr;2) of a digital adder (13) before being held by a first data holding circuit (14), a first reference value (D1) and a second reference value (D2) are compared, respectively, by a first data comparator (15) and a second data comparator (16), to thereby change one cycle of the output control of the pulse train fout from four cycles (T1-T4) to two cycles (T1-T2) of the reference clock. Further, by comparing the output (&thgr;1) of the first data holding circuit (14) and the first reference value (D1) by a third data comparator (19), the latch timing of the overflow signal is changed from T4 to T1.

Abstract: A clock generator for reproducing data recorded onto an optical disk, and more particularly, an apparatus for stably generating a clock signal synchronized with an input signal and a method of generating a clock signal. The apparatus generating a clock signal includes a voltage controlled oscillator, a phase compensator, a frequency compensator, and an adder. The voltage controlled oscillator generates a clock signal of a frequency that varies with a control voltage signal. The phase compensator receives an input signal and the clock signal, detects a phase difference between the input signal and the clock signal, and generates a first control voltage corresponding to the phase difference. The frequency compensator receives the input signal and the clock signal, detects a frequency difference between the input signal and the clock signal, and generates a second control voltage corresponding to the frequency difference.

Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Abstract: A double balanced mixer for mixing an RF input signal with a local oscillator signal to provide at an output an intermediate frequency signal with a high third order intercept point. A first and second local oscillator balun receives a local oscillator signal. A first and second RF balun receives a RF signal. A first mixer is coupled to the first local oscillator balun and the first RF balun. A second mixer is coupled in parallel with the first mixer. The second mixer is coupled to the second local oscillator balun and the second RF balun. The parallel coupled mixers provide an intermediate frequency signal. A first intermediate frequency balun is coupled to the first mixer and a second intermediate frequency balun is coupled to the second mixer. The mixer also has increased isolation.

Abstract: A programmable mixer includes a 1st mixing stage, a 2nd mixing stage, a coupling element, and a compensation module. The 1st mixing stage is operably coupled to mix one leg of a differential input signal with a differential local oscillation. The 2nd mixing stage is operably coupled to mix the other leg of the differential input with the differential local oscillation. The coupling element couples the 1st and 2nd mixing stages together. The compensation module is operably coupled to the 1st mixing stage and/or the 2nd mixing stage to modify the operational characteristics (e.g., current, impedance, gain, et cetera) of the 1st and/or 2nd mixing stages based on a control signal.

Abstract: A mixer of a communication system. The communication system has an antenna, low noise amplifier, a mixer, a local oscillator and an intermediate frequency filter. The mixer has a mixer circuit, a gain amplified circuit, a voltage auto-tracking circuit and a direct current voltage generating circuit. The direct current voltage generating circuit can reduce the output power of the local oscillator, extend the lifetime of the battery used in the mobile communication system, and reduce the distortion of harmonic wave of the local oscillator to reduce the noise figure of the mixer. Using the voltage auto tracking circuit and the gain amplified circuit, the linearity of the mixer is enhanced, and the conversion gain of the mixer is adjusted by varying the load resistors.

Abstract: A method is provided for generating a frequency stable wavelet. Initially, a first sine wave is generated having a first frequency. Then, a half sine wave window is generated having a window frequency. The first sine wave and the half sine wave window are then mixed to create the frequency stable wavelet. In this process the sine wave has a frequency greater than half sine wave window so that the half sine wave window covers more than a single sine pulse. The half wave window can be created by generating a second sine wave having a second frequency that is twice the window frequency, and then fully rectifying the second sine wave. The wavelets created in this manner can be used for a variety of purposes, including correlating with a received signal or transmitting as a wireless signal.

Abstract: Provided is a device for controlling a frequency response by scaling an impedance. The device includes a filter and a duty ratio controller. The filter generates an output signal after removing a frequency from an input signal, and comprises a first impedance component and a switch. The switch, which is serially connected to the first impedance component, is switched on or off in response to a duty-controlled clock signal. The duty ratio controller receives a clock signal, controls a duty ratio of the clock signal, and generates the duty-controlled clock signal. The duty ratio controller comprises a flip-flop, which has a clock terminal that receives the clock signal, and a reset terminal, which receives a delayed signal obtained after delaying the clock signal by a time delay. The duty ratio controller further comprises a delay component that receives the clock signal, generates the delayed signal, and controls the time delay in response to a duty control signal.

Abstract: Double balanced mixers having transistor pairs are affected by area mismatches between the transistors. The area mismatches can be represented as a ratio between the mixer core transistors that is directly related to voltage. Thus, an input voltage into one of the mixer core transistors in a transistor pair can compensate for the area mismatch. The compensation is achieved by a voltage track and hold feedback loop to one of the mixer core transistors.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

Abstract: A frequency converter configured to convert a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency is disclosed, which comprises an adder configured to add the first current signal and a predetermined reference current signal to output a third current signal corresponding to the sum of the first current signal and the reference current signal, and a switching circuit configured to pass only that portion of the third current signal which is larger in magnitude than a threshold current to output the second current signal.