Abstract: A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

Abstract: A receiving circuit includes: a first decision circuit to output boundary data obtained by performing a binary-decision on input data in synchronization with a first clock; a first decision feedback equalizer to output center data obtained by performing equalization and a binary-decision on the input data using a first equalization coefficient in synchronization with a second clock; a phase detection circuit to detect phase information of the input data based on the boundary data and the center data; a phase control circuit to output phase difference information of the center data based on an opening of an eye pattern formed by overlaying data transition patterns; a first phase adjustment circuit to adjust a phase of the first clock based on the phase information; and a second phase adjustment circuit to adjust a phase of the second clock based on the phase information and the phase difference information.

Abstract: A fractional PLL circuit includes a phase comparator, a voltage-controlled oscillation unit, a phase-selection unit equally dividing a period of an output-clock signal output from the voltage-controlled oscillation unit into a predetermined number of phases, selecting one of the phases, and generating a phase-shift clock signal having a rising edge in the selected phase, a frequency-divider unit dividing a frequency of the phase-shift clock signal and outputting the divided signal to the phase comparator, and a phase-control unit determining the phase to be selected for changing a duration of a period of the phase-shift clock signal by a predetermined phase-shift amount and controlling the phase-selection unit. The phase-control unit operates with the frequency-divided phase-shift clock signal.

Abstract: A noise-shaping time-to-digital converter has a large range and high resolution. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit to generate the phase-adjusted feedback signal based on the reference signal and the gating signal.

Abstract: A Method and Apparatus for Fast Frequency Acquisition in PLL System has been disclosed. In one implementation a time to digital converter is used with cycle slip detection for fast acquisition and lock. In one implementation cycle slip detection is applied to determine if a feedback clock from an oscillator is faster than a reference clock or not in one measurement cycle.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

Abstract: A semiconductor integrated circuit includes an identification information storage, an intermediate clock generator and an operating clock generator. The identification information storage stores identification information of the semiconductor integrated circuit. The intermediate clock generator generates an intermediate clock having a frequency higher than that of a reference clock using the reference clock input to the semiconductor integrated circuit from the outside of the semiconductor integrated circuit. The operating clock generator generates the operating clock having a frequency higher than that of the reference clock and lower than that of the intermediate clock in synchronization with a timing allotted according to the identification information stored in the identification information storage, using the intermediate clock.

Abstract: A current generating circuit, which comprises: a first capacitor, comprising a first terminal and a second terminal; a second capacitor, comprising a first terminal and a second terminal; a first charge adjusting path, arranged for adjusting charges of the first capacitor according to a first charge adjusting voltage; a second charge adjusting path, arranged for adjusting charges of the second capacitor according to the first charge adjusting voltage; and a current generating path, coupled to the first capacitor and the second capacitor, arranged for generating a target current based on a difference between a first voltage provided by the first capacitor and a second voltage provided by the second capacitor.

Abstract: An electronic circuit, includes: a first oscillator configured to generate a reference signal; a plurality of phase synchronization circuits, each including a second oscillator configured to generate an output signal having a frequency corresponding to an input, and a phase comparator configured to input, to the second oscillator, a signal corresponding to a phase difference between the output signal generated by the second oscillator and the reference signal generated by the first oscillator; and a controller configured to control relative phases of the reference signals input to the phase synchronization circuits from the first oscillator, based on the signals input to the corresponding second oscillators from the phase comparators in the phase synchronization circuits.

Abstract: Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed.

Abstract: A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.

Abstract: A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.

Abstract: A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.

Abstract: A clock generating device measures a frequency ratio between a clock signal (32.768 kHz+?) and a reference frequency value based on a clock signal (25 MHz); generates a clock signal obtained by masking a portion of clocks of the clock signal based on a measurement result of the frequency ratio; and updates a compensation value of a frequency temperature characteristic of the clock signal when a difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results is greater than a reference value of the frequency ratio.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal.

Abstract: A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.

Abstract: A circuit includes a logic circuit, first and second storage circuits, a timing detection circuit, and a compensation circuit. The logic circuit generates a digital value in response to a first periodic signal. The first storage circuit stores time information in response to a second periodic signal. The second storage circuit stores the digital value in response to the second periodic signal. The timing detection circuit generates a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value. The compensation circuit generates adjusted time information based on the time information stored in the first storage circuit and the detection signal.

Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.

Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Abstract: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.

Abstract: A high-frequency signal processing device having a frequency synthesizer (PLL: Phase Locked Loop) is provided. A control circuit measures oscillation frequencies obtained upon setting a bias current of an oscillation circuit to first and second bias setting values and acquires a frequency difference amount of the oscillation frequencies. The frequency difference amount may be acquired as difference amount of setting values of a coarse adjustment capacitance setting signal (CTRM) using, for example, an automatic frequency selector unit. The control circuit retains a relationship of a difference amount of bias setting values and a difference value of setting values of the CTRM and approximating the relationship to a linear function. Thereafter, the control circuit defines, upon switching the bias current during locking of the PLL, the CTRM based on the linear function and switches the CTRM together with the bias current.

Abstract: A PLL circuit includes a divider configured to generate a divided signal having a cycle of T/M (where M is an integer greater than or equal to two) by dividing an oscillation signal; a phase comparator configured to generate a phase comparison result by calculating an exclusive logical OR of M reference signals and the divided signal, the M reference signals having the cycle of T and respective time intervals shifted sequentially by T/2M; a loop filter configured to generate a voltage signal using the phase comparison result as input; and a voltage-controlled oscillator configured to generate the oscillation signal by oscillating at a frequency depending on the voltage signal.

Abstract: Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a range bounded by upper and lower limit values. The proportional component is combined with the integral component if the proportional component falls within the range to provide the phase error signal. Otherwise, the proportional component is modified to meet a phase slope requirement while leaving the integral component unmodified. The modified proportional component is combined with the unmodified integral component to provide the phase error signal.

Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.

Abstract: In a phase adjustment circuit, a first phase adjuster has a plurality of parallel-connected first inverters that receives an input signal to be phase-adjusted, wherein a first inverter to be activated is selected by a first control signal. A second phase adjuster has a plurality of parallel-connected second inverters that receives the input signal with a predetermined delay time, wherein a second inverter to be activated is selected by a second control signal. An output circuit receives output signals of the first and second phase adjusters and outputs a signal whose phase is adjusted within a range of the delay time. The second phase adjuster further includes transistors connected to the second inverters. During the delay time, these transistors block a current path between the first and second phase adjusters, under the control of the input signal.

Abstract: In accordance with an embodiment of the disclosure, systems and methods are provided for aligning signals in a timing recovery system. In certain implementations, a coarse phase error indicative of a phase offset between a reference signal and a signal is identified. The signal is transformed based at least in part on the coarse phase error, and operation of a phase-locked loop is initiated based at least in part on the coarse phase error.

Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Abstract: A phase-locked loop device is configured to manage a transition from a relaxation-oscillation mode to a random noise operation mode. It is designed for progressively reducing proportional and integral coefficients that are implemented in a loop filter of the PLL device. Recovering the last values formerly used for the proportional and integral coefficients is also provided, in case the PLL lock state is lost. Such transition management may be combined with using a voltage-controlled oscillator within the PLL device, which has several control inputs.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

Abstract: A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). The method generates a clock at frequency fs, and creates 2 sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. The method also generates a first tone signal s2(t) having a predetermined second frequency f2 outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating 2 digital sample signals per clock period 1/fs. The 2 digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of signals at a plurality of pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted signal's reflected signal as a tuning reference. It also describes using these techniques to align signals fed back from the target chips to the source chip.

Abstract: A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.

Abstract: A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which dynamically generates loop-filter parameters for the digital loop filter based on an observed pattern of up/down values from the phase-detector output over a specified period of time. A digitally controlled oscillator (DCO) receives the loop-filter output signal and produces a PLL output signal. Finally, a feedback path returns the PLL output signal to the phase detector.