Abstract: A circuit device includes an oscillation signal generation circuit that generates an oscillation signal by using a resonator and a processing circuit that estimates an aging characteristic of the oscillation frequency of the resonator based on the result of comparison between the phase of a reference signal based on a satellite signal transmitted from a navigation satellite and the phase of a clock signal based on the oscillation signal. The processing circuit estimates the aging characteristic based on an index value representing the reliability of the state of the received satellite signal and the result of the phase comparison.

Abstract: Disclosed herein is a control system for a laser scanning projector. The control system includes a mirror controller generating a mirror synchronization signal for an oscillating mirror apparatus based upon a mirror clock signal. The control system also includes laser modulation circuitry for generating a laser synchronization signal as a function of a laser clock signal, and generating control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry is for generating the laser clock signal and sending the laser clock signal to the laser modulation circuitry, receiving the mirror synchronization signal from the mirror controller, receiving the laser synchronization signal from the laser modulation circuitry, and modifying frequency and phase of the laser clock signal for the laser as a function of the mirror synchronization signal and the laser synchronization signal.

Abstract: A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.

Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.

Abstract: A multi-stop time-to-digital converter (TDC, 110) includes single-stop TDCs (510) connected to output nodes of a ring oscillator (504). Other features and embodiments are also provided.

Abstract: In a PLL circuit, a multi-band control oscillator includes multiple bands gradually increasing or decreasing a frequency in accordance with a control signal and being separated from each other, is capable of selectively switching one band among the multiple bands, and generates a signal of a frequency corresponding to the control signal in the band that is switched as a reference signal. A band setting unit sets the band of the multi-band control oscillator. The band setting unit sets the band for a present or subsequent time after a control command generator finishes outputting the control command to gradually increase or decrease from a previous start frequency to a previous stop frequency and before the control command generator starts outputting the control command to gradually increase or decrease from a present start frequency.

Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Abstract: The amount of drift in an oscillator, as a function of temperature, can be profiled by adjusting the temperature and monitoring the corresponding change in frequency of the oscillator. Temperature sensors on a computing device can provide the temperature readings for the profiling, as well as readings during operation. A system clock on the computing device can be synchronized with a reliable external clock at a regular interval, such as every fifteen minutes. Between those synchronizations, the temperature values provided by the temperature sensors can be determined and the corresponding oscillator drift determined according to the oscillator profile. The drift value can be used to adjust the output of the system clock to account for variations that may become present between the synchronization times. Effects of factors such as voltage and humidity can also be profiled to provide a more accurate timing signal.

Abstract: A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.

Abstract: A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

Abstract: A leakage current measurement circuit is provided. The leakage current measurement circuit includes a leakage generation circuit and a detection circuit. The leakage generation circuit generates a leakage current from a start time point and generates a leakage voltage signal having a voltage level that changes from an initial voltage based on the leakage current. The detection circuit generates a detection signal having an activation time, the detection signal being generated from the start time point to a detection time point, and the detection time point corresponding to when the voltage level of the leakage voltage signal reaches a target voltage.

Abstract: A display apparatus includes a display panel, a gate driving part, a data driving part and a voltage providing part. The display panel displays an image, and includes gate lines and data lines. The gate driving part outputs gate signals to the gate lines. The data driving part outputs data signals to the data lines through data channels, and outputs a dummy data signal through a dummy data channel adjacent to a side of the display panel. The voltage providing part provides a driving voltage to the data driving part, receives the dummy data signal, and controls the driving voltage provided to the data driving part based on a voltage difference of the dummy data signal according to a time of the dummy data signal.

Abstract: A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.

Abstract: A transceiver device includes a pulse generator, an output node, and an internal bus that couples the pulse generator and the output node. The pulse generator is configured to selectively add at least one pulse to an outlet power supply signal conveyed by the internal bus to the output node, wherein the pulse generator includes a bootstrap capacitor with a first side coupled to the internal bus and a second side selectively coupled to at least one current source. A transceiver method includes receiving an inlet power supply signal and providing an outlet power supply signal to an output node, wherein the outlet power supply signal is based on the inlet power supply signal. The transceiver method also includes selectively adding a sync or data pulse to the outlet power supply signal based on a pulse scheme and a bootstrap capacitor coupled to the output node.

Abstract: Presented are a system and method for distributing video over a network. The system includes a source that outputs video with a first frame rate, a transmitter, a receiver, and a sink. The transmitter receives video from the source and processes the video by encoding the video with frame boundary information, packetizing, and transmitting the video. The receiver includes a frame buffer, a timing generator, and a PLL. The receiver receives and processes the video by retrieving the frame boundary information, decoding the video into sub-frames, and writing the sub-frames to the buffer. All the processing occurs on sub-frame portions of the video in sub-frame time intervals. The receiver transmits video with a second frame rate to the sink. The timing generator generates output timing and uses the PLL to synchronize the output timing with the frame boundary information and synchronizes the first and second frame rates.

Abstract: An oscillator circuit includes an oscillating unit, a counter unit, and a set value generator. The oscillating unit is configured to output an oscillation signal having a frequency corresponding to an input frequency setting value. The counter unit is configured to count a number of pulses of the oscillation signal during a time period corresponding to a period of a reference signal input from outside. The set value generator is configured to generate the frequency setting value every predetermined time period based on the count of the pulses counted by the counter unit.

Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.

Abstract: A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a digital signal process on phase comparison result data which is a result of the phase comparison so as to generate frequency control data, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data. The processor performs the digital signal process by using data used when a hold-over state is ended in a case where the hold-over state occurs due to the absence or the abnormality of the reference signal, and then the hold-over state is ended.

Abstract: A circuit for receiving data is described. The circuit comprises a phase detector circuit comprising a detector having a first input configured to receive a sum of an oscillator phase and a phase error, and a second input coupled to an output of a first sample selector; a second sample selector having an input coupled to receive the input data and generate output data; and an eye detection circuit comprising a third sample selector having an input coupled to receive the input data and a comparator for comparing outputs of the second sample selector and the third sample selector to determine how much an eye is open for a plurality of channels. A method of implementing a receiver is also described.

Abstract: A semiconductor device including a selection section that selects and outputs one video signal from plural input video signals; a clock signal output section that outputs a clock signal that corresponds to the video signal selected by the selection section; and a masking section that, for a predetermined period starting from a point when the clock signal output from the clock signal output section is switched in accordance with a switching of the selection of the video signal, performs masking processing on a synchronization signal that, among plural synchronization signals that correspond respectively to the plural video signals, corresponds to the video signal selected by the selection section. The selection section outputs the selected video signal in synchronization with the synchronization signal that corresponds to the selected video signal and that has undergone masking processing.

Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.

Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

Abstract: A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.

Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Abstract: A time-to-digital converter including N stages of converting circuits, where N?2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.

Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal (SDLY1) at a first point (t1) in time and a second delay signal (SDLY2) at a second point in time (t2). The sampler module is configured to provide a first sample (S1) of the oscillator output signal (SOUT) at the first point in time (t1) and a second sample (S2) of the oscillator output signal (SOUT) at the second point in time (t2). The interpolator is configured to provide a sampler signal (SSAMPL) by interpolating the first sample (S1) and the second sample (S2). The voltage controlled oscillator is configured to control the oscillator output signal (SOUT) based on the sampler signal (SSAMPL).

Abstract: Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.

Abstract: A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

Abstract: A modem includes a modulator and a demodulator. The demodulator includes a direct current removing (DCR) circuit to transition between an acquisition mode, where the DCR circuit operates with a first loop gain; and a tracking mode, where the DCR circuit operates with a second loop gain. The second loop gain is smaller than the first loop gain, and the timing of the transition between the acquisition mode and tracking mode is programmable.

Abstract: A semiconductor device may be provided. The semiconductor device may operate in a 2N mode as well as a normal mode.

Abstract: A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.

Abstract: Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel. For this purpose, the clock output signals from the various independent blocks are first mutually aligned in proper order using a lower speed clock, and subsequently offset from one another such that sampling instances of the various sampler blocks are interleaved. Digitized data words corresponding to common input data and outputted by the various sampler blocks are compared after alignment of the clock output signals to correct additional timing misalignment between the multiple sampler blocks. The digitized data words need only be aligned once or at most infrequently after the clock output signals are aligned, since the additional timing misalignment is caused mainly path delays that are substantially invariant over time.

Abstract: A compensation circuit for an oven-controlled crystal oscillator serving as a reference for a phase-locked loop in holdover mode is disclosed. A non-linear function module generates a modified aging signal that is a non-linear function of an aging signal. A first Kalman filter generates an estimate of the frequency drift of the crystal oscillator based on the temperature signal. A second Kalman filter generates an estimate of the frequency drift based on the modified aging signal. A combining and comparing module combines the estimates generated by the first and second Kalman filters and compares the estimates with detected frequency drift to produce an error signal to update the Kalman filters. In holdover mode the Kalman filters generate an error signal to correct the oscillator frequency based on updates obtained during operation of the phase-locked loop in normal mode.

Abstract: A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.

Abstract: Embodiments herein describe a common point of control of local clocks in endpoint devices in a media production studio that are synchronized using an IP-based synchronization protocol. In one embodiment, a master clock generator outputs a master clock signal which is distributed to the endpoint devices in the media production studio. The endpoint devices include local clock generators that convert the master clock into an adjusted clock. A clock manager provides a common point of control for the local clock generators in the endpoints. The clock manager includes an input/output (I/O) interface which enables an engineer to adjust the jam time of the local clock generators as well as adjust a delay used when outputting media content to another endpoint device.

Abstract: An integrated circuit is disclosed that implements a phase-locked loop with charge scaling. In an example aspect, the integrated circuit includes a charge pump, a filter, and a charge manager. The charge pump generates a current signal, and the filter includes a filter capacitor. The charge manager is coupled between the charge pump and the filter. The charge manager includes current-sampling capacitance circuitry and a charge manager controller that is coupled to the current-sampling capacitance circuitry. The current-sampling capacitance circuitry receives the current signal from the charge pump and retains charge from the current signal to create stored charge, with the stored charge including a first charge portion and a second charge portion. The charge manager controller causes the current-sampling capacitance circuitry to communicate the first charge portion to the filter capacitor and causes the current-sampling capacitance circuitry to divert the second charge portion away from the filter capacitor.

Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.

Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

Abstract: An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.

Abstract: A display apparatus constituting a multi display system is provided. The display apparatus includes an input connector to receive input of an image, a processor to process an image corresponding to the display apparatus from the input image, a display to display the processed image, and an output connector to transmit the input image to an adjacent display apparatus connected to the display apparatus, and the processor, in response to an image input through the input connector being changed to a second connector from a first image, processes an image corresponding to the display apparatus from the second image, and controls the display to display the processed second image based on a synchronization signal of the first image.

Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

Abstract: The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.