Abstract: A Time-Average-Frequency direct period synthesizer is used to improve crystal-less frequency generator's frequency stability. It includes (a) a temperature sensor circuit to compensate temperature-induced frequency instability; (b) a voltage sensor circuit to compensate voltage-induced frequency instability; (c) a calibration circuit to correct manufacture-related frequency error; (d) a frequency control word update circuit to receive the temperature- and voltage-related frequency adjustments, and the calibration-related adjustment, to generate the corresponding frequency control word in a predetermined schedule; (f) a Time-Average-Frequency direct period synthesizer to receive said frequency control word in the predetermined schedule and produce a clock signal with a frequency that is stable and accurate by counteracting the frequency variation caused by crystal-less oscillators' temperature and voltage dependence and correcting the frequency error introduced in manufacture process.

Abstract: One bit is a smallest increment of binary measurement in first and second digital values. The first digital value is converted into a first analog signal. The second digital value is converted into a second analog signal. The first analog signal is augmented by a first amount that equates to less than the smallest increment of binary measurement, so that the augmented first analog signal by definition does not equal the second analog signal. The second analog signal is augmented by a second amount that equates to less than the smallest increment of binary measurement, so that the augmented second analog signal by definition does not equal the first analog signal. The augmented first analog signal is compared to the second analog signal, and a first signal is output in response thereto. The augmented second analog signal is compared to the first analog signal, and a second signal is output in response thereto.

Abstract: One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.

Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.

Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

Abstract: Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.

Abstract: A clock system receiving a reference clock signal via an alignment location and developing a functional clock signal provided to a functional circuit via a clock path. The clock system includes a low bandwidth PLL, a high bandwidth PLL, and a delay path. The low bandwidth PLL receives the reference clock signal and a feedback clock signal and provides a filtered clock signal. The high bandwidth PLL receives the filtered clock signal and provides the functional clock signal, and has a feedback input coupled to its output via a local feedback path. The delay path is coupled between the output of the low bandwidth PLL and the alignment location to provide the feedback clock signal to the low bandwidth PLL. The delay and clock paths are substantially matched. The bandwidths of the low and high bandwidth PLLs may be individually configured to reduce both input jitter and internal jitter, respectively.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.

Abstract: A system and a method for modulating an input signal are provided. The system includes a fractional-N phase locked loop (PLL) for frequency multiplying the input signal by a multiplication factor to generate an output signal. The fractional-N PLL includes an input signal path and a feedback signal path. The system includes a controllable delay line for inserting a linearizing tone into the input signal path or the feedback signal path of the fractional-N PLL.

Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

Abstract: A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.

Abstract: A disclosed exemplary embodiment is a phase locked loop comprising a main charge pump driven by a phase error signal, and providing a first input to a loop filter. An auxiliary charge pump driven by the phase error signal feeds a second input of the loop filter. The loop filter can be an active loop filter comprising an operational amplifier and a feedback RC network. The first input of the active loop filter can be an inverting input of the operational amplifier and the second input can be a non-inverting input of the operational amplifier. An on-chip stabilizing capacitor fed by the auxiliary charge pump and coupled to the second input of the loop filter is significantly smaller than the conventional stabilizing capacitors. The loop filter outputs a regulating voltage for regulating the oscillation frequency of a voltage controlled oscillator in the phase locked loop.

Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.

Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.

Abstract: A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.

Abstract: A PLL circuit that operates in synchronization with an operating clock and generates and outputs a generated clock in synchronization with an external clock, including a multi-phase clock generating unit that generates multi-phase clocks including n clocks which have a same frequency and differ in phase one another, one of the clocks in the multi-phase clock being the operating clock, a frequency signal generating unit that outputs a frequency signal based on a phase difference signal from a phase comparator, an oscillating unit that generates and outputs a clock oscillating with a frequency corresponding to the frequency signal, and the phase comparator that measures a time difference between rising times or falling times of the inputted external clock and the oscillating unit based on the n clocks in the multi-phase clocks, and outputs a phase difference signal indicating the time difference based on a result of the measurement.

Abstract: Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.

Abstract: A system for synchronizing a first clock and a second clock includes a receiver associated with the first clock, configured to receive a remote pulse from the second clock. The remote pulse has a pulse repetition frequency and spectral characteristics that are known to the local clock. The system also includes a local pulse emitter configured to create a local pulse at the first clock, and optics configured to align the local pulse and the remote pulse. The system further includes an interferometer configured to create an interference pattern between the local pulse and the remote pulse. A controller is provided that is configured to calculate a time delay between the first clock and the second clock based on the interference pattern between the local pulse and the remote pulse.

Abstract: An apparatus includes a reference clock signal generator circuit configured to generate a reference clock signal in response to a carrier signal and a clock selection signal generator circuit configured to generate a clock selection signal in response to the carrier signal. The apparatus further includes a multiplexer (MUX) circuit configured to selectively output the reference clock signal and a PLL output clock signal in response to the clock selection signal and a phase-locked loop (PLL) circuit configured to receive the selectively output signal between the reference clock signal and the PLL output clock signal at a reference input thereof and to generate the PLL output clock signal therefrom. An ISO 14443 type A smart card may include such apparatus.

Abstract: Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract: Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract: In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: A clock generating circuit includes a phase detector for detecting a phase difference between a first clock and a second clock to generate a detecting result associated with the phase difference, a first filtering device for filtering the detecting result, a charge pump for generating a control signal according to the filtered detecting result, a second filtering device for filtering the control signal, and a controllable oscillator for generating an output clock according to the filtered control signal, wherein the output clock is utilized to generate the second clock.

Abstract: A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal.

Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. The inputs to the QTF may be either single input, multiple outputs, or alternatively, multiple inputs, multiple outputs. Furthermore, the second state of either of the two QTF transformations may be either positive or negative. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications.

Abstract: A fractional-N frequency synthesizer having an exact output frequency and phase includes a phase locked loop including a phase detector responsive to a reference signal and a fractional divider. The phase locked loop has an output signal whose frequency is a fractional multiple of the input reference signal. The synthesizer also includes a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number.

Abstract: A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF.

Abstract: In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A method of tuning the frequency of a generated signal to form an output signal including: forming the generated signal at a signal generator; comparing a feedback signal with a reference signal and generating a control signal in dependence on that comparison, wherein the feedback signal is generated using the output signal; and generating the output signal by performing a frequency-dividing operation in dependence on the generated signal and a dividing factor, wherein the dividing factor is determined in dependence on the control signal.

Abstract: Disclosed herein is a semiconductor device that includes: an input node; an output node; a plurality of variable delay circuits connected in series between the input node and the output node; a control circuit that commonly controls delay amounts of the variable delay circuits based on phases of a first clock signal supplied to the input node and a second clock signal output from the output node; and a mixer circuit that generates a third clock signal based on any one of input clock signals respectively input to the variable delay circuits and any one of output clock signals respectively output from the variable delay circuits.

Abstract: A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

Abstract: The circuit for the clocking of an FPGA comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; and a digitally controlled oscillator, which outputs a clocking signal for the FPGA, wherein the FLL-circuit is designed in order to register a first number of clocking signals from the digitally controlled oscillator during a second number of periods of the reference clock, the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of the digitally controlled oscillator.

Abstract: A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

Abstract: A receiving circuit includes: a sampling circuit to sample input data in synchronization with first clock to obtain boundary data, and sample the input data in synchronization with second clock to obtain center data; a decision feedback equalizer to perform equalization on the center data using an equalization coefficient, and output first output data; a first comparator circuit to perform binary decision on the boundary data and output second output data; a phase detection circuit to detect phase information of the input data using the first output data and the second output data; a phase difference computation circuit to calculate phase difference of the first output data using the equalization coefficient; a first phase adjustment circuit to adjust phase of the first clock using the phase information; and a second phase adjustment circuit to adjust phase of the second clock using the phase information and the phase difference.

Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.

Abstract: Apparatuses and methods for delaying signals using a delay circuit are described. An example apparatus includes a controller configured to set a delay length. The example apparatus further includes a delay circuit coupled to the controller. The delay circuit may include active delay stages of a plurality of delay stages that are configured to delay a first signal based on the delay length. Based on an increase to the delay length, the delay circuit is further configured to activate another delay stage of the plurality of delay stages responsive to a second signal that is based on the first signal.

Abstract: A spread spectrum transmission circuit includes a phase locked loop composed of a filter. The phase locked loop generates a series of incremental control signals and decreasing control signals based on the frequency difference and phase difference between a reference clock signal and a feedback signal. The circuit further has a frequency locked loop an amplitude locked loop, a digital-analog converter, an injection current source, an extraction current source, a multiplexer is connected to the locked phase loop and a rail-to-rail digital signal generator having an input connected to the multiplexer and an output connected to inputs of the locked frequency loop and the locked amplitude loop.

Abstract: A phase-locked loop circuit including a lock detector is provided comprising a delay circuit including a load capacitor, and a bias circuit configured to generate a constant reference current, wherein the load capacitor is charged or discharged with a current whose level is dependent upon the reference current.

Abstract: A spread-spectrum clock generator includes a frequency comparator, for generating a compensation signal according to a reference signal and a frequency signal corresponding to an output frequency signal; a triangle-wave generator, for generating a triangle-wave signal according to a frequency control signal; an adder, coupled between the triangle-wave generator and the frequency comparator, for adding the compensation signal to the triangle-wave signal to generate an addition result; and a frequency synthesizer, coupled between the frequency comparator and the adder, for generating the output frequency signal to adjust the output frequency signal according to the addition result so as to reduce a shift of the output frequency signal.

Abstract: In part, the invention relates to an optical coherence tomography system that includes one or more phased-locked loop circuits. In one embodiment, the phased-locked loop circuit includes a phase detector, a loop filter, and a voltage controlled oscillator wherein the phased-locked loop circuit is configured to generate a sample clock. The optical coherence tomography system can include an analog to digital converter having a sample clock input, an interferometric signal input, and a sample data output, the analog to digital converter configured to receive the sample clock and sample OCT data in response thereto. In one embodiment, the phased-locked loop circuit is configured to lock on a first signal in less than or equal to about 1 microseconds.